FPGA-Neural

T

micheleandClaude Sonnet 5 95849c9002 docs: certify SPI slave/engine (C.7), confirm len=0 is properly guarded

Certified via existing extensive pre-session coverage (10 tests in
spi_engine_tb.v, CDC ratio-variation test in spi_slave_tb.v, explicit
unknown-opcode-as-NOP handling), re-confirmed passing in Phase 0.

Targeted check given this campaign's recurring pattern (missing
zero-value guards, BUG-002 through 006): WRITE_RAM/READ_RAM len=0 IS
explicitly guarded (rtl/spi_engine.v:817, transitions to ST_IGNORE) --
confirms the project does not systematically lack these guards, the
gap is specific to the modules already flagged.

No new bugs found in this aspect.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-04 14:54:56 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: certify SPI slave/engine (C.7), confirm len=0 is properly guarded

2026-09-04 14:54:56 +02:00

rtl

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

2026-09-04 10:16:31 +02:00

sim

test: certify graph_engine gather/guard (C.6), find related BUG-006