micheleandClaude Sonnet 5
03b5cbc25b
Follow-up to EXP-0051: built sdram_controller_pipelined.v, remapping addr->bank to low-order bits (today's weight region always maps to bank 0) and adding a shadow-slot ACTIVATE lookahead so a different-bank request can start its tRCD wait during the current transaction's tail. Phase A (isolated tb_sdram_controller_pipelined.v, 38/38 bit-exact, independently re-verified this session): mechanism works, saves exactly 2 cycles (tRCD) per different-bank back-to-back pair, matching the theoretical ceiling derived before measuring (CAS_LATENCY+BURST_LEN are serial on the shared data bus regardless of bank, so more than tRCD/tRP was never on the table). Phase B (integration, tb_nms_dstress_sdram_pipelined.v, independently rebuilt/rerun): N=4 49760 cycles (-0.33% vs baseline), N=8 49755 (-0.31%) -- both 256/256 bit-exact. Root cause of the gap: the W port's request/ready protocol is one-at-a-time, so a second, different-bank request is essentially never already pending while the first is still in flight, so the mechanism rarely triggers in the real system even though it's correct when directly stimulated. Not integrated into production; kept as additive reference for a possible future arbiter/backend pipelined-dispatch rewrite (out of scope here, larger and riskier). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YHENedK76onD2Vtc2CMjej
256 lines
11 KiB
Verilog
256 lines
11 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXPERIMENTAL fork of sdram_unified_backend.v -- the ONLY change is
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// instantiating sdram_controller_pipelined.v instead of sdram_
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// controller.v. W-port cache, arbitration, and the W/AR top-level FSM
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// are ALL byte-for-byte unchanged. See sdram_controller_pipelined.v's
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// own header for what changed at the controller level and why, and
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// hardware/v2/logs/experiments.log (search "pipelin") for why this
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// fork exists: testing whether bank-interleaved command pipelining
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// recovers any of the ~77-78% Bank-W busy ceiling EXP-0051 measured.
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// ============================================================
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module sdram_unified_backend_pipelined #(
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parameter ADDR_WIDTH = 26,
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parameter CLK_FREQ_MHZ = 64,
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parameter W_ENTRIES = 4,
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parameter ROW_BITS = 13,
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parameter COL_BITS = 10,
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parameter BANK_BITS = 2
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)(
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input wire clk,
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input wire rst,
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input wire w_req,
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input wire [ADDR_WIDTH-1:0] w_addr,
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output reg [63:0] w_rdata,
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output reg w_ready,
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input wire ar_req,
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input wire ar_wr,
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input wire [ADDR_WIDTH-1:0] ar_addr,
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input wire [15:0] ar_wdata,
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input wire ar_lb_n,
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input wire ar_ub_n,
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output reg [15:0] ar_rdata,
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output reg ar_ready,
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output wire sdram_cke,
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output wire sdram_cs_n,
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output wire sdram_ras_n,
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output wire sdram_cas_n,
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output wire sdram_we_n,
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output wire [BANK_BITS-1:0] sdram_ba,
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output wire [ROW_BITS-1:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output wire [1:0] sdram_dqm
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);
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initial if (ADDR_WIDTH != BANK_BITS + ROW_BITS + COL_BITS + 1) begin
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$display("FATAL sdram_unified_backend_pipelined: ADDR_WIDTH(%0d) != BANK_BITS(%0d)+ROW_BITS(%0d)+COL_BITS(%0d)+1",
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ADDR_WIDTH, BANK_BITS, ROW_BITS, COL_BITS);
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$finish;
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end
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localparam WEIDXW = (W_ENTRIES <= 1) ? 1 : $clog2(W_ENTRIES);
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reg w_cache_valid [0:W_ENTRIES-1];
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reg [ADDR_WIDTH-1:0] w_cache_addr [0:W_ENTRIES-1];
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reg [63:0] w_cache_data [0:W_ENTRIES-1];
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reg [WEIDXW-1:0] w_alloc_ptr;
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wire [W_ENTRIES-1:0] w_match_oh;
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genvar wgi;
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generate
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for (wgi = 0; wgi < W_ENTRIES; wgi = wgi + 1) begin : GEN_WMATCH
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assign w_match_oh[wgi] = w_cache_valid[wgi] && (w_cache_addr[wgi] == w_addr);
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end
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endgenerate
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reg w_hit_found_c;
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reg [WEIDXW-1:0] w_hit_idx_c;
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integer ei;
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generate
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if (W_ENTRIES == 4) begin : GEN_WHIT_FLAT
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always @(*) begin
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w_hit_found_c = |w_match_oh;
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casez (w_match_oh)
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4'b1???: w_hit_idx_c = 2'd3;
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4'b01??: w_hit_idx_c = 2'd2;
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4'b001?: w_hit_idx_c = 2'd1;
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4'b0001: w_hit_idx_c = 2'd0;
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default: w_hit_idx_c = {WEIDXW{1'b0}};
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endcase
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end
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end else begin : GEN_WHIT_FALLBACK
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always @(*) begin
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w_hit_found_c = 1'b0;
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w_hit_idx_c = {WEIDXW{1'b0}};
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for (ei = 0; ei < W_ENTRIES; ei = ei + 1) begin
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if (w_cache_valid[ei] && w_cache_addr[ei] == w_addr) begin
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w_hit_found_c = 1'b1;
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w_hit_idx_c = ei[WEIDXW-1:0];
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end
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end
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end
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end
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endgenerate
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wire w_cache_hit = w_hit_found_c && w_req;
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reg ctrl_req;
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reg ctrl_wr;
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reg [ADDR_WIDTH-2:0] ctrl_addr;
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reg [127:0] ctrl_wdata;
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reg [15:0] ctrl_wmask;
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wire [127:0] ctrl_rdata;
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wire ctrl_ready;
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wire ctrl_busy;
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sdram_controller_pipelined #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(8),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_sdram_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr),
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.wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
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);
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localparam S_IDLE = 3'd0,
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S_W_WAIT = 3'd1,
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S_AR_RD_WAIT = 3'd2,
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S_AR_WR_WAIT = 3'd3;
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reg [2:0] state;
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reg w_pending_upper_half;
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reg [ADDR_WIDTH-1:0] w_pending_addr;
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reg [2:0] ar_pending_word;
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reg w_req_pending;
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reg [ADDR_WIDTH-1:0] w_req_addr_lat;
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reg ar_req_pending;
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reg ar_req_wr_lat;
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reg [ADDR_WIDTH-1:0] ar_req_addr_lat;
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reg [15:0] ar_req_wdata_lat;
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reg ar_req_lbn_lat, ar_req_ubn_lat;
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wire w_eff_req = w_req || w_req_pending;
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wire [ADDR_WIDTH-1:0] w_eff_addr = w_req ? w_addr : w_req_addr_lat;
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wire ar_eff_req = ar_req || ar_req_pending;
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wire ar_eff_wr = ar_req ? ar_wr : ar_req_wr_lat;
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wire [ADDR_WIDTH-1:0] ar_eff_addr = ar_req ? ar_addr : ar_req_addr_lat;
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wire [15:0] ar_eff_wdata= ar_req ? ar_wdata : ar_req_wdata_lat;
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wire ar_eff_lbn = ar_req ? ar_lb_n : ar_req_lbn_lat;
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wire ar_eff_ubn = ar_req ? ar_ub_n : ar_req_ubn_lat;
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wire [ADDR_WIDTH-2:0] w_eff_aligned_word_addr = {w_eff_addr[ADDR_WIDTH-1:4], 3'b000};
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wire w_eff_addr_is_upper_half = w_eff_addr[3];
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wire [ADDR_WIDTH-2:0] ar_eff_block_base = {ar_eff_addr[ADDR_WIDTH-2:3], 3'b000};
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wire [2:0] ar_eff_word_in_blk = ar_eff_addr[2:0];
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integer ri;
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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for (ri = 0; ri < W_ENTRIES; ri = ri + 1) w_cache_valid[ri] <= 1'b0;
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w_alloc_ptr <= {WEIDXW{1'b0}};
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ctrl_req <= 1'b0; ctrl_wr <= 1'b0; ctrl_addr <= {(ADDR_WIDTH-1){1'b0}};
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ctrl_wdata <= 128'h0; ctrl_wmask <= 16'hFFFF;
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w_ready <= 1'b0; w_rdata <= 64'h0;
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ar_ready <= 1'b0; ar_rdata <= 16'h0;
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w_pending_upper_half <= 1'b0; w_pending_addr <= {ADDR_WIDTH{1'b0}};
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ar_pending_word <= 3'h0;
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w_req_pending <= 1'b0; w_req_addr_lat <= {ADDR_WIDTH{1'b0}};
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ar_req_pending <= 1'b0; ar_req_wr_lat <= 1'b0;
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ar_req_addr_lat <= {ADDR_WIDTH{1'b0}}; ar_req_wdata_lat <= 16'h0;
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ar_req_lbn_lat <= 1'b1; ar_req_ubn_lat <= 1'b1;
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end else begin
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ctrl_req <= 1'b0;
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w_ready <= 1'b0;
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ar_ready <= 1'b0;
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if (w_req) begin
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w_req_addr_lat <= w_addr;
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w_req_pending <= 1'b1;
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end
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if (ar_req) begin
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ar_req_wr_lat <= ar_wr;
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ar_req_addr_lat <= ar_addr;
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ar_req_wdata_lat <= ar_wdata;
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ar_req_lbn_lat <= ar_lb_n;
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ar_req_ubn_lat <= ar_ub_n;
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ar_req_pending <= 1'b1;
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end
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case (state)
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S_IDLE: begin
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if (w_cache_hit) begin
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w_rdata <= w_cache_data[w_hit_idx_c];
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w_ready <= 1'b1;
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w_cache_valid[w_hit_idx_c] <= 1'b0;
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w_req_pending <= 1'b0;
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end else if (w_eff_req) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b0;
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ctrl_addr <= w_eff_aligned_word_addr;
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ctrl_wmask <= 16'h0000;
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w_pending_upper_half <= w_eff_addr_is_upper_half;
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w_pending_addr <= w_eff_addr;
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w_req_pending <= 1'b0;
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state <= S_W_WAIT;
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end else if (ar_eff_req && !ar_eff_wr) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b0;
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ctrl_addr <= ar_eff_block_base;
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ctrl_wmask <= 16'h0000;
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ar_pending_word <= ar_eff_word_in_blk;
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ar_req_pending <= 1'b0;
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state <= S_AR_RD_WAIT;
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end else if (ar_eff_req && ar_eff_wr) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b1;
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ctrl_addr <= ar_eff_block_base;
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ctrl_wdata <= {8{ar_eff_wdata}};
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ctrl_wmask <= {16{1'b1}} & ~(16'h0003 << (ar_eff_word_in_blk*2)) | ({14'b0, ar_eff_ubn, ar_eff_lbn} << (ar_eff_word_in_blk*2));
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ar_req_pending <= 1'b0;
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state <= S_AR_WR_WAIT;
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end
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end
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S_W_WAIT: begin
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if (ctrl_ready) begin
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if (w_pending_upper_half) begin
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w_rdata <= ctrl_rdata[127:64];
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w_cache_data[w_alloc_ptr] <= ctrl_rdata[63:0];
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w_cache_addr[w_alloc_ptr] <= w_pending_addr - {{(ADDR_WIDTH-4){1'b0}}, 4'd8};
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end else begin
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w_rdata <= ctrl_rdata[63:0];
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w_cache_data[w_alloc_ptr] <= ctrl_rdata[127:64];
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w_cache_addr[w_alloc_ptr] <= w_pending_addr + {{(ADDR_WIDTH-4){1'b0}}, 4'd8};
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end
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w_cache_valid[w_alloc_ptr] <= 1'b1;
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w_alloc_ptr <= (w_alloc_ptr == W_ENTRIES[WEIDXW-1:0]-1'b1) ? {WEIDXW{1'b0}} : w_alloc_ptr + 1'b1;
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w_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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S_AR_RD_WAIT: begin
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if (ctrl_ready) begin
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ar_rdata <= ctrl_rdata[ar_pending_word*16 +: 16];
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ar_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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S_AR_WR_WAIT: begin
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if (ctrl_ready) begin
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ar_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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