micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
105 lines
5.2 KiB
Markdown
105 lines
5.2 KiB
Markdown
# FPGA-Neural V2 — PINOUT
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FPGA: **LFE5U-45F-8BG381** (ECP5U, speed grade -8)
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Package: **CABGA381**
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Frozen top-level: `nms_neural_multiprocessor_sdram_unified` (N_SLOTS=4)
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**Single external memory: ONE SDRAM (AS4C4M16SA-6TIN). No PSRAM, no
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second memory device anywhere in this design (STEP19/DEC-0034).**
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## Status: SDRAM pinout REAL and P&R-verified; host bus still BLOCKED
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Correction to an earlier draft of this document: the real Lattice
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pinout data source (`FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv`, rev 3.0)
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IS available on this machine (`~/Downloads/`), and its own summary
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(`docs/pinouts.md`, repo root) already lists real, exact JTAG/config/
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power ball assignments for CABGA381 — found during this step's own
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pre-commit `git status` review, not assumed missing without checking.
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`hardware/v2/constraints/v2_unified.lpf` now contains a REAL,
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P&R-verified ball assignment for clk/rst (39 total) and the full
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37-signal SDRAM bus, sourced directly from that CSV (bank 6/7 plain-
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GPIO pads, avoiding PLL/PCLK-reserved balls) — confirmed by a real
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nextpnr-ecp5 run: all 37 SDRAM signals placed successfully, "110
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warnings" (exactly the 110 still-unconstrained host-bus signals, a
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clean cross-check that the inventory below is complete and accurate).
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**This has NOT been electrically cross-verified** (VCCIO6/7 bank
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voltage vs the SDRAM's own LVCMOS33 requirement, signal integrity,
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trace-length matching for the 16-bit DQ bus) — it is a real, sourced,
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P&R-confirmed CANDIDATE assignment, not a board-signed-off pinout.
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## Real ball assignments now in place
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| Signal | Ball | Source |
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|---|---|---|
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| `clk` | H5 | Reused from V1's own real, validated LPF |
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| `rst` | B4 | Reused from V1's own real, validated LPF |
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| `sdram_cke`/`cs_n`/`ras_n`/`cas_n`/`we_n` | B5/C5/C4/A3/B3 | Real CSV, bank 7 |
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| `sdram_ba[1:0]` | E4, C3 | Real CSV, bank 7 |
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| `sdram_a[11:0]` | D5,D3,F4,E5,E3,F5,A2,B1,C2,C1,D2,D1 | Real CSV, bank 7 |
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| `sdram_dq[15:0]` | E1,G5,H3,J5,K3,K2,H1,J1,K1,K4,L4,L5,M5,M4,N4,N5 | Real CSV, banks 7/6 |
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| `sdram_dqm[1:0]` | P5, N3 | Real CSV, bank 6 |
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Full detail: `hardware/v2/constraints/v2_unified.lpf`.
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Real JTAG/config/power balls (from `docs/pinouts.md`, not yet
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transcribed into the LPF since this design's own top-level does not
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expose them as RTL ports — they are implicit ECP5 device pins):
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TDI=R5, TCK=T5, TMS=U5, TDO=V4 (bank 40); PROGRAMN=W3, INITN=V3,
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DONE=Y3, CCLK=U3 (bank 8); VCC balls (1.1V) at H8-N13 cluster;
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VCCAUX (2.5V) at F6/P6/F15/P15; VCCIO0-8 bank assignments listed in
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`docs/pinouts.md`.
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## Signal inventory (real, from the frozen top-level's own port list)
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Total top-level I/O: **149 signals**, cross-checked exactly against
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the real POST-P&R `TRELLIS_IO: 149/245` figure (STEP19) — a real
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**45-pin reduction** from STEP18's dual-memory design (194 pins),
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exactly matching the removed PSRAM interface's own pin count.
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| Group | Count | Ball assignment |
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|---|---|---|
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| Clock/reset (`clk`, `rst`) | 2 | **Real, assigned** (H5, B4) |
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| Host/control (`reg_*`) | 110 | **BLOCKER — see below** |
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| SDRAM (`sdram_*`) | 37 | **Real, assigned, P&R-verified** |
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| **Total** | **149** | matches P&R exactly |
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## CRITICAL finding: the "host" interface is not a physical interface
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**110 of 149 pins (73.8%) are the raw `reg_*` job-registration bus** —
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a simulation/testbench convenience, not a real board protocol. No RTL
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exists to serialize this for physical use. Ball assignment for these
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110 signals is deliberately NOT attempted yet, even though real GPIO
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balls are available (46+ more plain-GPIO candidates remain in banks
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6/7 alone after the 37 used above) — assigning pins to an interface
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that must be redesigned first would be premature, wasted work. **This
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remains the single largest real BLOCKER to physical realization.**
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## I/O standard / bank assignment
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LVCMOS33 assumed and used in the LPF above for all 39 real-assigned
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signals — matches `docs/pinouts.md`'s own real VCCIO range (1.2–3.3V)
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and V1's own real, validated board convention. Real per-bank voltage
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compatibility for banks 6/7 specifically (used for SDRAM) has not been
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independently re-verified against the SDRAM device's own datasheet
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this round (WARNING, not BLOCKER — LVCMOS33 is a reasonable, likely-
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correct default, not yet double-checked).
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## Configuration pins (JTAG/config)
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Now REAL and known (see table above) — `docs/pinouts.md`'s own
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summary of the same official CSV. This closes what was previously
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documented as a blocker for THESE specific pins; only the general-
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purpose host-bus assignment (unrelated to JTAG/config) remains open.
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## Summary
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| Item | Status |
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| Real ball-level LPF for the SDRAM interface | **Done — 37/37 signals, P&R-verified** |
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| Real ball-level assignment for clk/rst | **Done — reused from V1** |
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| Real ECP5U-45F CABGA381 ball-map data source | **Found — `~/Downloads/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv`, summarized in `docs/pinouts.md`** |
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| Aggregate I/O feasibility (149/245 fits the package) | Confirmed, real POST-P&R |
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| Real JTAG/config/power ball identification | **Done — see `docs/pinouts.md`** |
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| Physical host interface RTL | **BLOCKER — does not exist (110 raw pins, no serializer, no ball assignment)** |
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| I/O standard/bank electrical cross-check | WARNING — LVCMOS33 assumed, not independently re-verified per bank |
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