micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
89 lines
4.5 KiB
Markdown
89 lines
4.5 KiB
Markdown
# FPGA-Neural V2 — OPEN ITEMS
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Consolidated from HARDWARE_FREEZE.md, PINOUT.md, CLOCK_ARCHITECTURE.md,
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POWER_ARCHITECTURE.md, SCHEMATIC_READINESS.md. Classified per the
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governing spec's own rule: BLOCKER / CRITICAL / WARNING / OPEN /
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FUTURE.
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## BLOCKER (impede la realizzazione o il funzionamento del chip)
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1. **No physical host interface exists.** The RTL's own "host" ports
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are a 110-pin raw parallel job-registration bus
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(`reg_valid`/`reg_node_id`/`reg_required`/`reg_producer_ids`/
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`reg_x_base`/`reg_w_base`/`reg_n_tiles`/`reg_result_addr`) — a
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simulation/testbench convenience, not a real board protocol. No
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RTL exists to serialize it (e.g. SPI, matching V1's own
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`spi_neuron_top.v` precedent).
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2. **The 110-pin host/registration bus has no real ball assignment**
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(deliberately — it is not yet a real physical protocol, see item 1).
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The SDRAM bus (37 signals) and clk/rst (2 signals) now DO have a
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real, sourced, P&R-verified assignment (`hardware/v2/constraints/
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v2_unified.lpf`, from the real Lattice pinout CSV found at
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`~/Downloads/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv` during this
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step's own pre-commit review) — this item is narrower than
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originally scoped.
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3. **No schematic exists; no PCB has been started.**
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## CRITICAL (rischio elevato, deve essere risolto prima del freeze)
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1. **Timing closure is MARGINAL, with an unfavorable pass rate.** 8
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real P&R seeds for the frozen N=4 single-SDRAM design: only 1/8
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reach ≥80MHz (66.97–81.84MHz range). This is WORSE than STEP18's
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own dual-memory design (5/8 pass). The critical path itself is
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unchanged (still `dependency_manager.v`'s own pre-existing
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`first_ready_idx`/`reg_ready` chain) — the regression is attributed
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to added overall die/routing pressure from consolidation, not a new
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RTL defect, but it is real and unresolved.
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2. **Clock source/oscillator gap.** The RTL requires a direct ≥80MHz
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clock (no PLL exists anywhere in the hierarchy — confirmed via
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`EHXPLLL: 0/4` in every real synthesis run). Prior project memory
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records a 16MHz board oscillator. Neither "source an 80MHz+
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oscillator" nor "add a real PLL to the RTL" has been decided.
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3. **Two physical memories were required through STEP18** — RESOLVED
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this round (DEC-0034): the V2 physical path no longer instantiates
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`hardware/v1/rtl/psram_controller.v` at all. Kept here only as a
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closed CRITICAL item for the historical record.
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## WARNING (non blocca il prototipo ma deve essere documentato)
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1. N=2's real Fmax (86.04MHz in STEP18's own dual-memory design) and
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the STEP19 single-SDRAM N=2 config were not both measured with the
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same best-of-N-seed rigor as N=4 — a real, disclosed gap in
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measurement thoroughness, not a functional issue.
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2. `W_ENTRIES`/cache sizing in the weight-fetch path was set to match
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`N_SLOTS` (4) by construction reasoning, not swept for optimality.
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3. I/O standard (LVCMOS33 assumed for all 149 signals) has not been
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verified per real VCCIO bank once ball assignment becomes possible.
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## OPEN (decisione ancora da prendere)
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1. Configuration-flash part number / SPI-flash-boot vs JTAG-only
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bring-up.
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2. Power regulator topology and part numbers (the previously-recorded
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`../basic-ecp5-pcb` reference design is not accessible this
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session to confirm as a concrete plan).
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3. Real current budget (requires running a real power-estimation tool
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against the actual synthesized netlist — not done this round).
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4. Decoupling/bulk capacitance values (depend on regulator selection).
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5. Reset synchronization to a real external POR/supervisor source.
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6. Real per-bank VCCIO/I-O-standard verification once ball data is
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available.
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## FUTURE EVOLUTION (miglioramento post-freeze — explicitly deferred)
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1. N=8 evaluation.
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2. A smarter W/AR priority scheme in `sdram_unified_backend.v` to
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recover some of the +10.8% (N=4) / +5.1% (N=2) cycle-count cost of
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single-SDRAM unification (STEP18 EXP-0046's own packing win is
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still present — this is about the NEW W-vs-AR contention specifically).
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generic
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3. Page-mode / keep-row-open SDRAM controller redesign (STEP18's own
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identified next bottleneck for raw memory bandwidth, independent of
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the single-vs-dual-memory question).
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4. True multi-outstanding SDRAM request pipelining (STEP18 Part E's
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own documented, deliberately out-of-scope boundary).
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5. A real physical host-interface RTL bridge (SPI or similar),
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resolving BLOCKER #1 above.
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6. Floorplanning / seed-pinning work to convert the current MARGINAL
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timing result into a reliable PASS.
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