micheleandClaude Sonnet 5
7e2711fa27
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top, mem_arbiter, int8_memory_access, memory_interface, psram_controller, memory_model) and every testbench that mirrors it, so the system's byte-address space reaches the full 8 MiB the recommended PSRAM part (ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3) actually provides -- previously only 4 MiB (half the chip) was reachable, since int8_memory_access.v's byte->word address shift (addr >> 1) turned the old 22-bit byte address into only 21 real word bits, one short of the chip's real 22-bit word address (A0-A21). At 23 bits, that same shift lands exactly on all 22 chip address lines, so the whole part is usable now instead of deferred to a future widening. Also fixes a stray 22'd11-sized literal in layer_sequencer.v's descriptor-table address increment (numerically already safe via Verilog's zero-extension, but now correctly unsized so it always matches ADDR_WIDTH instead of silently assuming 22). Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field note (23 bits, top 1 reserved bit instead of 2) and docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has one spare address line" framing is gone now that all 22 are wired and used). Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a Yosys elaboration check of spi_neuron_top with the new default and no override) passes clean. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
788 lines
19 KiB
Verilog
788 lines
19 KiB
Verilog
`timescale 1ns/1ps
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 16;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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// ============================================================
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// CLOCK / RESET
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// ============================================================
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reg clk;
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reg rst;
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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// ============================================================
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// NEURON MEMORY
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// ============================================================
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reg start;
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reg [ADDR_WIDTH-1:0] x_base;
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reg [ADDR_WIDTH-1:0] w_base;
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reg [ADDR_WIDTH-1:0] bias_addr;
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reg [15:0] n_inputs_real;
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wire signed [7:0] y;
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wire busy;
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wire done;
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// neuron_memory -> memory_interface
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wire neuron_mem_req;
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wire neuron_mem_wr;
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wire [ADDR_WIDTH-1:0] neuron_mem_addr;
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wire signed [7:0] neuron_mem_wdata;
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wire signed [7:0] neuron_mem_rdata;
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wire neuron_mem_ready;
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// ============================================================
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// TB PRELOAD MASTER
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//
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// Direct 16-bit master.
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// Used only before starting neuron_memory.
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// ============================================================
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reg tb_mem_req;
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reg tb_mem_wr;
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reg [ADDR_WIDTH-1:0] tb_mem_addr;
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reg [DATA_WIDTH-1:0] tb_mem_wdata;
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reg tb_mem_lb_n;
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reg tb_mem_ub_n;
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wire [DATA_WIDTH-1:0] tb_mem_rdata;
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wire tb_mem_ready;
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// ============================================================
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// SINGLE MASTER MUX
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//
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// 0 = TB preload master
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// 1 = neuron_memory master
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// ============================================================
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reg use_neuron_master;
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wire master_req;
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wire master_wr;
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wire [ADDR_WIDTH-1:0] master_addr;
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wire [DATA_WIDTH-1:0] master_wdata;
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wire master_lb_n;
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wire master_ub_n;
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// ============================================================
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// MEMORY INTERFACE
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// ============================================================
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wire [DATA_WIDTH-1:0] memory_rdata;
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wire memory_ready;
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wire memory_mem_req;
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wire memory_mem_wr;
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wire [ADDR_WIDTH-1:0] memory_mem_addr;
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wire [DATA_WIDTH-1:0] memory_mem_wdata;
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wire memory_mem_lb_n;
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wire memory_mem_ub_n;
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wire [DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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assign master_req =
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use_neuron_master ? neuron_mem_req : tb_mem_req;
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assign master_wr =
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use_neuron_master ? neuron_mem_wr : tb_mem_wr;
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assign master_addr =
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use_neuron_master ? (neuron_mem_addr >> 1) : tb_mem_addr;
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assign master_wdata =
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use_neuron_master
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? (neuron_mem_addr[0]
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? {neuron_mem_wdata, 8'h00}
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: {8'h00, neuron_mem_wdata})
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: tb_mem_wdata;
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assign master_lb_n =
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use_neuron_master
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? (neuron_mem_addr[0] ? 1'b1 : 1'b0)
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: tb_mem_lb_n;
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assign master_ub_n =
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use_neuron_master
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? (neuron_mem_addr[0] ? 1'b0 : 1'b1)
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: tb_mem_ub_n;
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// Return path
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assign tb_mem_rdata = memory_rdata;
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assign tb_mem_ready = memory_ready;
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assign neuron_mem_rdata =
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neuron_mem_addr[0]
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? memory_rdata[15:8]
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: memory_rdata[7:0];
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assign neuron_mem_ready = memory_ready;
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) u_memory_if (
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.clk(clk),
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.rst(rst),
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.req(master_req),
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.wr(master_wr),
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.addr(master_addr),
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.wdata(master_wdata),
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.lb_n(master_lb_n),
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.ub_n(master_ub_n),
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.rdata(memory_rdata),
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.ready(memory_ready),
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.mem_req(memory_mem_req),
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.mem_wr(memory_mem_wr),
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.mem_addr(memory_mem_addr),
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.mem_wdata(memory_mem_wdata),
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.mem_lb_n(memory_mem_lb_n),
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.mem_ub_n(memory_mem_ub_n),
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.mem_rdata(psram_mem_rdata),
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.mem_ready(psram_mem_ready)
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);
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// ============================================================
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// PSRAM PHYSICAL INTERFACE
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// ============================================================
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n;
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wire psram_oe_n;
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wire psram_we_n;
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wire psram_lb_n;
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wire psram_ub_n;
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wire psram_zz_n;
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// ============================================================
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// PSRAM CONTROLLER
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// ============================================================
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.CLK_FREQ_MHZ(80)
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) u_psram_ctrl (
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.clk(clk),
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.rst(rst),
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.mem_req(memory_mem_req),
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.mem_wr(memory_mem_wr),
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.mem_addr(memory_mem_addr),
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.mem_wdata(memory_mem_wdata),
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.mem_lb_n(memory_mem_lb_n),
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.mem_ub_n(memory_mem_ub_n),
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.mem_rdata(psram_mem_rdata),
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.mem_ready(psram_mem_ready),
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.psram_a(psram_a),
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.psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n),
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.psram_oe_n(psram_oe_n),
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.psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n),
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.psram_ub_n(psram_ub_n),
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.psram_zz_n(psram_zz_n)
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);
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// ============================================================
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// PSRAM MODEL
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// ============================================================
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(16384)
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) u_psram (
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.clk(clk),
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.a(psram_a),
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.dq(psram_dq),
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.ce_n(psram_ce_n),
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.oe_n(psram_oe_n),
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.we_n(psram_we_n),
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.lb_n(psram_lb_n),
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.ub_n(psram_ub_n),
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.zz_n(psram_zz_n)
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);
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// ============================================================
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// NEURON MEMORY
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// ============================================================
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neuron_memory #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(8),
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.N_INPUTS(32),
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.N_NEURONS(1),
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.PARALLEL(8),
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.ACC_WIDTH(32)
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) u_neuron (
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.clk(clk),
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.rst(rst),
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.start(start),
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.mem_req(neuron_mem_req),
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.mem_wr(neuron_mem_wr),
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.mem_addr(neuron_mem_addr),
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.mem_wdata(neuron_mem_wdata),
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.mem_rdata(neuron_mem_rdata),
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.mem_ready(neuron_mem_ready),
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.x_base(x_base),
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.w_base(w_base),
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.bias_addr(bias_addr),
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.n_inputs_real(n_inputs_real),
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.y_bus(y),
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.busy(busy),
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.done(done)
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);
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// ============================================================
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// TB WORD WRITE
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//
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// Directly through:
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//
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// TB -> memory_interface -> psram_controller -> PSRAM
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//
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// No force.
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// ============================================================
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task tb_write_word;
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input [ADDR_WIDTH-1:0] addr_i;
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input [15:0] data_i;
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begin
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@(posedge clk);
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tb_mem_addr <= addr_i;
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tb_mem_wdata <= data_i;
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tb_mem_wr <= 1'b1;
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tb_mem_lb_n <= 1'b0;
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tb_mem_ub_n <= 1'b0;
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tb_mem_req <= 1'b1;
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@(posedge clk);
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tb_mem_req <= 1'b0;
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wait (tb_mem_ready);
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@(posedge clk);
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end
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endtask
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// ============================================================
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// PRELOAD 32 INT8 VALUES
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//
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// Two INT8 values per PSRAM word.
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// ============================================================
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task preload_vector;
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input [ADDR_WIDTH-1:0] base;
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input signed [7:0] value;
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integer k;
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begin
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for (k = 0; k < 32; k = k + 2) begin
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tb_write_word( (base >> 1) + (k >> 1), {value, value} );
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end
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end
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endtask
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// ============================================================
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// PRELOAD WEIGHTS
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// ============================================================
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task preload_weights;
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input [ADDR_WIDTH-1:0] base;
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input signed [7:0] value;
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integer k;
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begin
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for (k = 0; k < 32; k = k + 2) begin
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tb_write_word( (base >> 1) + (k >> 1), {value, value} );
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end
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end
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endtask
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task preload_x_pattern;
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input [ADDR_WIDTH-1:0] base;
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integer k;
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reg signed [7:0] v0;
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reg signed [7:0] v1;
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begin
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for (k = 0; k < 32; k = k + 2) begin
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v0 = k + 1;
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v1 = k + 2;
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tb_write_word(
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(base >> 1) + (k >> 1),
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{v1, v0}
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);
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end
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end
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endtask
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// ============================================================
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// PRELOAD BIAS
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// ============================================================
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task preload_bias;
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input [ADDR_WIDTH-1:0] addr_i;
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input signed [7:0] value;
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begin
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// Bias address is a BYTE address.
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// Write a full word containing bias in low byte.
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tb_write_word(
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addr_i >> 1,
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{8'h00, value}
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);
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end
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endtask
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// ============================================================
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// PRELOAD `len` INT8 VALUES (for n_inputs_real < 32 tests)
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// ============================================================
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task preload_vector_n;
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input [ADDR_WIDTH-1:0] base;
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input signed [7:0] value;
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input integer len;
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integer k;
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begin
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for (k = 0; k < len; k = k + 2) begin
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tb_write_word( (base >> 1) + (k >> 1), {value, value} );
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end
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end
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endtask
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// ============================================================
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// RUN NEURON (timed variant: returns elapsed cycles via $time)
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// ============================================================
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integer t_start_nm, t_done_nm;
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task run_neuron_timed;
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input signed [7:0] expected;
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input [127:0] test_name;
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output integer elapsed_cycles;
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begin
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@(posedge clk);
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start <= 1'b1;
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t_start_nm = $time;
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@(posedge clk);
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start <= 1'b0;
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wait (done);
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t_done_nm = $time;
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elapsed_cycles = (t_done_nm - t_start_nm) / CLK_PERIOD;
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if (y !== expected) begin
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$display("");
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$display("FAIL %s", test_name);
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$display(" got = %0d (0x%02x)", y, y);
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$display(" expected = %0d (0x%02x)", expected, expected);
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$fatal;
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end else begin
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$display("PASS %-16s y=%0d (0x%02x), %0d cycles", test_name, y, y, elapsed_cycles);
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end
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@(posedge clk);
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end
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endtask
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// ============================================================
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// RUN NEURON
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// ============================================================
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task run_neuron;
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input signed [7:0] expected;
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input [127:0] test_name;
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begin
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@(posedge clk);
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start <= 1'b1;
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@(posedge clk);
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start <= 1'b0;
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wait (done);
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if (y !== expected) begin
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$display("");
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$display("FAIL %s", test_name);
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$display(
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" got = %0d (0x%02x)",
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y,
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y
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);
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$display(
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" expected = %0d (0x%02x)",
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expected,
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expected
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);
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$fatal;
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end else begin
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$display(
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"PASS %-16s y=%0d (0x%02x)",
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test_name,
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y,
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y
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);
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end
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@(posedge clk);
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end
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endtask
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// ============================================================
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// TEST
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// ============================================================
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integer i;
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integer cycles_full_nm, cycles_reduced_nm;
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initial begin
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// --------------------------------------------------------
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// Initial values
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// --------------------------------------------------------
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start = 1'b0;
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x_base = 22'h000000;
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w_base = 22'h000100;
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bias_addr = 22'h000200;
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n_inputs_real = 32;
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tb_mem_req = 1'b0;
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tb_mem_wr = 1'b0;
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tb_mem_addr = 0;
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tb_mem_wdata = 0;
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tb_mem_lb_n = 1'b1;
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tb_mem_ub_n = 1'b1;
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use_neuron_master = 1'b0;
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rst = 1'b1;
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// --------------------------------------------------------
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// VCD
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// --------------------------------------------------------
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$dumpfile("sim/neuron_memory.vcd");
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$dumpvars(0, tb);
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repeat (5)
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@(posedge clk);
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rst = 1'b0;
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// --------------------------------------------------------
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// Wait PSRAM initialization
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// --------------------------------------------------------
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wait (u_psram_ctrl.state == u_psram_ctrl.STATE_IDLE);
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$display("");
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$display("========================================");
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$display("NEURON MEMORY END-TO-END TEST");
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$display("========================================");
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$display("");
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// ========================================================
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// PRELOAD PHASE
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//
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// TB is the ONLY memory master.
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// ========================================================
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$display("PRELOAD: X = 1..32");
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preload_x_pattern(
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x_base
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);
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$display("PRELOAD: W = 1");
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preload_weights(
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w_base,
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8'sd1
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);
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$display("PRELOAD: BIAS = 0");
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preload_bias(
|
|
bias_addr,
|
|
8'sd0
|
|
);
|
|
|
|
// ========================================================
|
|
// HAND OVER MEMORY BUS
|
|
//
|
|
// From this point neuron_memory is the only master.
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b1;
|
|
|
|
$display("");
|
|
$display("MEMORY MASTER -> neuron_memory");
|
|
$display("");
|
|
|
|
// ========================================================
|
|
// TEST 0 - PATTERN
|
|
//
|
|
// X = 1..32
|
|
// W = 1
|
|
// BIAS = 0
|
|
//
|
|
// SUM = 1 + 2 + ... + 32 = 528
|
|
// Output saturates to 127.
|
|
// ========================================================
|
|
|
|
run_neuron(
|
|
8'sd127,
|
|
"PATTERN X=1..32"
|
|
);
|
|
|
|
// ========================================================
|
|
// RESTORE ORIGINAL VECTOR
|
|
//
|
|
// X = 1
|
|
// W = 1
|
|
// BIAS = 0
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b0;
|
|
|
|
preload_vector(
|
|
x_base,
|
|
8'sd1
|
|
);
|
|
|
|
preload_weights(
|
|
w_base,
|
|
8'sd1
|
|
);
|
|
|
|
preload_bias(
|
|
bias_addr,
|
|
8'sd0
|
|
);
|
|
|
|
use_neuron_master = 1'b1;
|
|
|
|
// ========================================================
|
|
// TEST 1
|
|
//
|
|
// 32 * 1 * 1 + 0 = 32
|
|
// ========================================================
|
|
|
|
run_neuron(
|
|
8'sd32,
|
|
"SUM=32"
|
|
);
|
|
|
|
// ========================================================
|
|
// TEST 2
|
|
//
|
|
// 32 * 1 * 4 = 128
|
|
// Saturated to 127.
|
|
//
|
|
// We must return control to TB to modify weights.
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b0;
|
|
|
|
preload_weights(
|
|
w_base,
|
|
8'sd4
|
|
);
|
|
|
|
preload_bias(
|
|
bias_addr,
|
|
8'sd0
|
|
);
|
|
|
|
use_neuron_master = 1'b1;
|
|
|
|
run_neuron(
|
|
8'sd127,
|
|
"SATURATION"
|
|
);
|
|
|
|
// ========================================================
|
|
// TEST 3
|
|
//
|
|
// 32 * 1 * (-1) = -32
|
|
// ReLU -> 0
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b0;
|
|
|
|
preload_weights(
|
|
w_base,
|
|
-8'sd1
|
|
);
|
|
|
|
preload_bias(
|
|
bias_addr,
|
|
8'sd0
|
|
);
|
|
|
|
use_neuron_master = 1'b1;
|
|
|
|
run_neuron(
|
|
8'sd0,
|
|
"RELU"
|
|
);
|
|
|
|
// ========================================================
|
|
// TEST 4
|
|
//
|
|
// 32 * 1 * 1 + 10 = 42
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b0;
|
|
|
|
preload_weights(
|
|
w_base,
|
|
8'sd1
|
|
);
|
|
|
|
preload_bias(
|
|
bias_addr,
|
|
8'sd10
|
|
);
|
|
|
|
use_neuron_master = 1'b1;
|
|
|
|
run_neuron(
|
|
8'sd42,
|
|
"BIAS=10"
|
|
);
|
|
|
|
// ========================================================
|
|
// TEST 5 - n_inputs_real < N_INPUTS (runtime early
|
|
// termination through the full memory stack)
|
|
//
|
|
// Full-width baseline: X=1 (32x), W=1, bias=0 -> 32
|
|
// Reduced: n_inputs_real=8, X=1 (8x), W=1, bias=0 -> 8,
|
|
// and must complete in fewer cycles (fewer RAM reads).
|
|
// ========================================================
|
|
|
|
use_neuron_master = 1'b0;
|
|
preload_vector(x_base, 8'sd1);
|
|
preload_weights(w_base, 8'sd1);
|
|
preload_bias(bias_addr, 8'sd0);
|
|
use_neuron_master = 1'b1;
|
|
|
|
run_neuron_timed(8'sd32, "FULL-WIDTH(32)", cycles_full_nm);
|
|
|
|
use_neuron_master = 1'b0;
|
|
preload_vector_n(x_base, 8'sd1, 8);
|
|
preload_vector_n(w_base, 8'sd1, 8);
|
|
preload_bias(bias_addr, 8'sd0);
|
|
use_neuron_master = 1'b1;
|
|
|
|
n_inputs_real = 8;
|
|
run_neuron_timed(8'sd8, "REDUCED(8)", cycles_reduced_nm);
|
|
n_inputs_real = 32;
|
|
|
|
if (cycles_reduced_nm >= cycles_full_nm) begin
|
|
$display("FAIL: n_inputs_real=8 run (%0d cycles) not faster than full-width (%0d cycles)", cycles_reduced_nm, cycles_full_nm);
|
|
$fatal;
|
|
end else begin
|
|
$display("PASS n_inputs_real early termination: %0d cycles vs %0d full-width", cycles_reduced_nm, cycles_full_nm);
|
|
end
|
|
|
|
// ========================================================
|
|
// FINAL
|
|
// ========================================================
|
|
|
|
$display("");
|
|
$display("========================================");
|
|
$display("NEURON MEMORY TEST PASSED");
|
|
$display("========================================");
|
|
$display("PSRAM -> INT8 -> NEURON : PASS");
|
|
$display("PATTERN X=1..32 : PASS");
|
|
$display("SUM : PASS");
|
|
$display("BIAS : PASS");
|
|
$display("ReLU : PASS");
|
|
$display("SATURATION : PASS");
|
|
$display("========================================");
|
|
$display("");
|
|
|
|
$finish;
|
|
|
|
end
|
|
|
|
endmodule |