micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
8 lines
1.1 KiB
CSV
8 lines
1.1 KiB
CSV
n_slots,variant,fmax_mhz,pass_80mhz,lut4,ccu2c,ff,dsp,bit_exact,total_cycles,classification
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4,original (nms_activation_fill_ctrl.v),55.22,FAIL,2937,705,5877,32,PASS,184771,POST-P&R MEASURED + RTL SIM (EXP-0028/STEP13)
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4,v2 (max_n_tiles registered once),72.78,FAIL,n/a,n/a,n/a,32,n/a,n/a,POST-P&R MEASURED (EXP-0030) -- real improvement (+31.8%) but insufficient alone
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4,v3 (2-stage: tag-equality/masking THEN max-fold),106.81,PASS,2776,705,5957,32,PASS,184771,POST-P&R MEASURED + RTL SIM bit-exact 256/256 (EXP-0030) -- ADOPTED
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1,v3,142.92,PASS,n/a,n/a,n/a,8,n/a,n/a,POST-P&R MEASURED (EXP-0030, carried from actfix1 build -- v3 not independently re-measured at N=1, expected >=v2's N=1 result)
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2,v3,n/a,PASS(inferred),n/a,n/a,n/a,16,PASS,185270,RTL SIM bit-exact, cycles identical to pre-fix baseline (EXP-0030) -- zero regression confirmed
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8,v3,52.25,FAIL,4653,1367,10855,64,PASS,184771,POST-P&R MEASURED (EXP-0031, exploratory) + RTL SIM bit-exact (EXP-0030-class run) -- DSP/LUT/FF all feasible, Fmax fails: same O(N_SLOTS) max-fold chain reappears at 2x depth, not yet re-pipelined for N=8
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