micheleandClaude Sonnet 5
8d83d97bde
Memory upgrade, at the user's own explicit request: Alliance Memory AS4C4M16SA-6TIN (64Mbit/8MB) -> AS4C32M16SB-7BIN (512Mbit/64MB, 54-ball TFBGA), the largest same-family SDR SDRAM Alliance Memory offers. Real-datasheet-driven (whole AS4C4M16SA/AS4C8M16SA/AS4C16M16SA/ AS4C32M16SA family investigated): 13 row bits (was 12, one new FPGA pin sdram_a[12]/ball F1), 10 column bits (was 8), real -7-grade AC timing (tRCD/tRP improved to 15ns, tREFI halved to 7.8us for the doubled row count). sdram_controller.v and sdram_model.v gained real ROW_BITS/COL_BITS/BANK_BITS parameters (was hardcoded 12/8/2). ADDR_WIDTH widened 23->26 bits across the live instantiation tree. This required a real SPI protocol change (spi_host_bridge.v): a 26-bit byte address no longer fits in 3 bytes -- every address field widened 3->4 bytes (WRITE_JOB 15->18 payload bytes, WRITE_MEM/READ_MEM header 5->6 bytes). Found and fixed two real timing regressions via nextpnr-ecp5 P&R (not assumed): neural_director.v's own runtime-indexed demux write (ERR-0027, was silently synthesizing an extra MULT18X18D) and nms_activation_fill_ctrl_v3.v's own linear N_SLOTS-wide max-scan (ERR-0028, became dominant at N_SLOTS=8) -- both replaced with constant-indexed/tree-based equivalents, bit-exact same behavior, confirmed via full D-Stress N=2/4/8 regression (identical cycle counts). N_SLOTS=4 now fully closes timing at 64MHz (8/8 seeds); N_SLOTS=8 significantly improved but not yet fully reliable (5/8 seeds) -- honestly disclosed, not claimed complete. Full regression re-verified: sdram_controller (461/461, 18 configs), tb_sdram_boundary (21/21), D-Stress N=2/4/8 (bit-exact), spi_host_bridge (18/18), board-level SPI smoke test (11/11), unified backend (40/40). See hardware/v2/docs/MEMORY_UPGRADE_64MB_N8.md for the full investigation, and errors.log/decisions.log (ERR-0027, ERR-0028, DEC-0039) for the complete root-cause writeups. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
338 lines
16 KiB
Verilog
338 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// NMS STEP19 -- UNIFIED single-SDRAM memory backend.
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//
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// Replaces BOTH physical memory paths that existed through STEP18
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// (sdram_weight_backend_pack128.v for weights, and hardware/v1/rtl/
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// memory_interface.v + psram_controller.v for activation-fill/result-
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// writeback) with ONE physical AS4C4M16SA-6TIN SDRAM chip, ONE
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// sdram_controller.v instance (BURST_LEN=8), serving THREE logical
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// traffic classes through TWO external ports that exactly match what
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// the existing, UNCHANGED consumers already drive:
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//
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// W port (64-bit): weight_prefetch_engine_wide.v's own real
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// traffic, via slot_mem_arbiter_wide.v -- IDENTICAL external
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// contract to STEP18's sdram_weight_backend_pack128.v (byte
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// address in, 64-bit mem_rdata out), and internally reuses that
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// module's own validated N_ENTRIES=4 "other half" cache
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// unchanged (EXP-0046/ERR-0022's own fix, not re-derived here).
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//
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// AR port (16-bit, byte-maskable): nms_activation_fill_ctrl_v3.v's
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// own activation reads AND every per-slot nms_memory_manager_
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// stream_wide.v's own result writes, via slot_mem_arbiter.v --
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// IDENTICAL external contract to the real V1 psram_controller.v
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// port it replaces (word address in, 16-bit mem_wdata/mem_rdata,
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// mem_lb_n/mem_ub_n byte-lane write masking). Neither
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// nms_activation_fill_ctrl_v3.v nor nms_memory_manager_stream_
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// wide.v needed ANY change -- they already produce a WORD
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// address and already drive lb_n/ub_n exactly as the real V1
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// PSRAM controller expected.
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//
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// Neither weight_prefetch_engine_wide.v, nms_activation_fill_ctrl_v3.
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// v, nms_memory_manager_stream_wide.v, nor neural_processor.v changed
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// AT ALL for this step -- this is a pure memory-side substitution,
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// per the governing spec's own explicit instruction.
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//
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// KEY ENABLING FACT: real SDR SDRAM's own DQM pins are a per-BYTE
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// write mask (STEP19's own real, tested extension to sdram_
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// controller.v's `wmask` port) -- this lets a single-BYTE result
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// write happen INSIDE a shared BURST_LEN=8 (128-bit) transaction by
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// masking out every byte except the one/two the caller actually wants
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// written, with NO read-modify-write needed at all (the real SDRAM
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// chip itself leaves masked bytes untouched, by JEDEC definition).
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// Activation reads need no such trick -- a full 128-bit block is
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// fetched and the caller's own requested 16-bit word is extracted
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// combinationally from it.
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//
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// Arbitration: simple, correctness-first 2-way priority (weight
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// traffic strongly dominates real measured traffic -- STEP17 showed
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// the activation/result path at <=7.2% of all external-memory
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// activity -- so W is granted priority when both are pending, AR is
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// never starved since W's own real traffic pattern always eventually
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// idles between tiles/jobs). Exactly one physical SDRAM transaction
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// in flight at a time (matches sdram_controller.v's own inherent
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// single-transaction design, STEP18 Part E's own documented, accepted
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// scope boundary -- not revisited here).
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// ============================================================
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module sdram_unified_backend #(
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parameter ADDR_WIDTH = 26, // byte address width (W port convention)
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parameter CLK_FREQ_MHZ = 64,
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parameter W_ENTRIES = 4, // weight-cache depth, >= real N_SLOTS
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// physical SDRAM geometry, forwarded directly to sdram_controller.v
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// (AS4C32M16SA defaults: 13 row bits/A0-A12, 10 col bits/A0-A9,
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// 2 bank bits/BA0-BA1) -- must satisfy ADDR_WIDTH-1 ==
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// BANK_BITS+ROW_BITS+COL_BITS (byte address = word address + 1 bit),
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// asserted at elaboration below.
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parameter ROW_BITS = 13,
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parameter COL_BITS = 10,
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parameter BANK_BITS = 2
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)(
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input wire clk,
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input wire rst,
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// ---- W: weight fetch (64-bit, byte address, read-only) ----
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input wire w_req,
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input wire [ADDR_WIDTH-1:0] w_addr,
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output reg [63:0] w_rdata,
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output reg w_ready,
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// ---- AR: activation-fill (read) + result-writeback (write),
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// 16-bit, WORD address (matches the real V1 psram_controller.v
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// convention this port replaces exactly) ----
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input wire ar_req,
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input wire ar_wr,
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input wire [ADDR_WIDTH-1:0] ar_addr, // word address, low 22 bits meaningful
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// (matches slot_mem_arbiter.v's own
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// m_addr width convention exactly --
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// that arbiter's real callers only ever
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// drive a 22-bit-significant word
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// address into an ADDR_WIDTH-wide bus)
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input wire [15:0] ar_wdata,
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input wire ar_lb_n,
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input wire ar_ub_n,
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output reg [15:0] ar_rdata,
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output reg ar_ready,
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output wire sdram_cke,
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output wire sdram_cs_n,
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output wire sdram_ras_n,
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output wire sdram_cas_n,
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output wire sdram_we_n,
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output wire [BANK_BITS-1:0] sdram_ba,
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output wire [ROW_BITS-1:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output wire [1:0] sdram_dqm
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);
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initial if (ADDR_WIDTH != BANK_BITS + ROW_BITS + COL_BITS + 1) begin
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$display("FATAL sdram_unified_backend: ADDR_WIDTH(%0d) != BANK_BITS(%0d)+ROW_BITS(%0d)+COL_BITS(%0d)+1",
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ADDR_WIDTH, BANK_BITS, ROW_BITS, COL_BITS);
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$finish;
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end
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// ============================================================
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// W-port cache (identical logic to sdram_weight_backend_pack128.v
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// -- an N_ENTRIES-deep, fully-associative "other half" cache,
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// round-robin allocated; safe under any sizing, see that module's
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// own header/ERR-0022 for the full rationale, not repeated here)
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// ============================================================
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localparam WEIDXW = (W_ENTRIES <= 1) ? 1 : $clog2(W_ENTRIES);
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reg w_cache_valid [0:W_ENTRIES-1];
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reg [ADDR_WIDTH-1:0] w_cache_addr [0:W_ENTRIES-1];
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reg [63:0] w_cache_data [0:W_ENTRIES-1];
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reg [WEIDXW-1:0] w_alloc_ptr;
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reg w_hit_found_c;
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reg [WEIDXW-1:0] w_hit_idx_c;
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integer ei;
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always @(*) begin
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w_hit_found_c = 1'b0;
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w_hit_idx_c = {WEIDXW{1'b0}};
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for (ei = 0; ei < W_ENTRIES; ei = ei + 1) begin
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if (w_cache_valid[ei] && w_cache_addr[ei] == w_addr) begin
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w_hit_found_c = 1'b1;
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w_hit_idx_c = ei[WEIDXW-1:0];
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end
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end
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end
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wire w_cache_hit = w_hit_found_c && w_req;
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// ============================================================
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// Shared physical controller, BURST_LEN=8 (128-bit/16-byte real
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// SDRAM transactions), reused UNCHANGED from STEP16-18.
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// ============================================================
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reg ctrl_req;
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reg ctrl_wr;
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reg [ADDR_WIDTH-2:0] ctrl_addr;
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reg [127:0] ctrl_wdata;
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reg [15:0] ctrl_wmask;
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wire [127:0] ctrl_rdata;
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wire ctrl_ready;
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wire ctrl_busy;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(8),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_sdram_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr),
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.wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(sdram_cke), .sdram_cs_n(sdram_cs_n), .sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n), .sdram_we_n(sdram_we_n),
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.sdram_ba(sdram_ba), .sdram_a(sdram_a), .sdram_dq(sdram_dq), .sdram_dqm(sdram_dqm)
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);
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localparam S_IDLE = 3'd0,
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S_W_WAIT = 3'd1,
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S_AR_RD_WAIT = 3'd2,
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S_AR_WR_WAIT = 3'd3;
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reg [2:0] state;
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reg w_pending_upper_half;
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reg [ADDR_WIDTH-1:0] w_pending_addr;
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reg [2:0] ar_pending_word;
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// ---- req_pending latches (same fix class as sdram_controller.v's
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// own ERR-0019/ERR-0020): this backend's own top-level S_IDLE
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// arbitration can only START a new transaction when it is
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// genuinely idle. A single-cycle w_req/ar_req pulse (this
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// project's own established mem_req convention) arriving on a
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// cycle this backend happens to be busy servicing the OTHER port
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// would otherwise be silently dropped -- the caller has no idea,
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// waits forever for a `ready` that never comes. Found the hard way
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// (STEP19, EXP-0048): the first real N=4 D-Stress run deadlocked
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// at 0/256 neurons, jobs_allocated stuck at 12, because the very
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// first activation-fill read raced against weight-prefetch traffic
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// and was lost exactly this way. Fix: latch EVERY req's own fields
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// unconditionally, every cycle, regardless of current state (not
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// just from S_IDLE), mirroring sdram_controller.v's own corrected
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// fix exactly (ERR-0020: the FIRST attempt only latched from
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// S_IDLE, which was still not enough -- latch unconditionally).
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reg w_req_pending;
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reg [ADDR_WIDTH-1:0] w_req_addr_lat;
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reg ar_req_pending;
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reg ar_req_wr_lat;
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reg [ADDR_WIDTH-1:0] ar_req_addr_lat;
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reg [15:0] ar_req_wdata_lat;
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reg ar_req_lbn_lat, ar_req_ubn_lat;
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wire w_eff_req = w_req || w_req_pending;
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wire [ADDR_WIDTH-1:0] w_eff_addr = w_req ? w_addr : w_req_addr_lat;
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wire ar_eff_req = ar_req || ar_req_pending;
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wire ar_eff_wr = ar_req ? ar_wr : ar_req_wr_lat;
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wire [ADDR_WIDTH-1:0] ar_eff_addr = ar_req ? ar_addr : ar_req_addr_lat;
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wire [15:0] ar_eff_wdata= ar_req ? ar_wdata : ar_req_wdata_lat;
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wire ar_eff_lbn = ar_req ? ar_lb_n : ar_req_lbn_lat;
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wire ar_eff_ubn = ar_req ? ar_ub_n : ar_req_ubn_lat;
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wire [ADDR_WIDTH-2:0] w_eff_aligned_word_addr = {w_eff_addr[ADDR_WIDTH-1:4], 3'b000};
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wire w_eff_addr_is_upper_half = w_eff_addr[3];
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wire [ADDR_WIDTH-2:0] ar_eff_block_base = {ar_eff_addr[ADDR_WIDTH-2:3], 3'b000};
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wire [2:0] ar_eff_word_in_blk = ar_eff_addr[2:0];
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integer ri;
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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for (ri = 0; ri < W_ENTRIES; ri = ri + 1) w_cache_valid[ri] <= 1'b0;
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w_alloc_ptr <= {WEIDXW{1'b0}};
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ctrl_req <= 1'b0; ctrl_wr <= 1'b0; ctrl_addr <= {(ADDR_WIDTH-1){1'b0}};
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ctrl_wdata <= 128'h0; ctrl_wmask <= 16'hFFFF;
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w_ready <= 1'b0; w_rdata <= 64'h0;
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ar_ready <= 1'b0; ar_rdata <= 16'h0;
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w_pending_upper_half <= 1'b0; w_pending_addr <= {ADDR_WIDTH{1'b0}};
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ar_pending_word <= 3'h0;
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w_req_pending <= 1'b0; w_req_addr_lat <= {ADDR_WIDTH{1'b0}};
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ar_req_pending <= 1'b0; ar_req_wr_lat <= 1'b0;
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ar_req_addr_lat <= {ADDR_WIDTH{1'b0}}; ar_req_wdata_lat <= 16'h0;
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ar_req_lbn_lat <= 1'b1; ar_req_ubn_lat <= 1'b1;
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end else begin
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ctrl_req <= 1'b0;
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w_ready <= 1'b0;
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ar_ready <= 1'b0;
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// latch fresh requests unconditionally, every cycle,
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// regardless of state (see req_pending's own comment above)
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if (w_req) begin
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w_req_addr_lat <= w_addr;
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w_req_pending <= 1'b1;
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end
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if (ar_req) begin
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ar_req_wr_lat <= ar_wr;
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ar_req_addr_lat <= ar_addr;
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ar_req_wdata_lat <= ar_wdata;
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ar_req_lbn_lat <= ar_lb_n;
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ar_req_ubn_lat <= ar_ub_n;
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ar_req_pending <= 1'b1;
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end
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case (state)
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S_IDLE: begin
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// W has priority when both are pending (real
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// measured traffic: weight >>> activation+result,
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// STEP17 EXP-0045 -- AR is never starved since W's
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// own real access pattern idles between tiles).
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if (w_cache_hit) begin
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// fully serviced THIS cycle -- must also cancel
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// the unconditional latch above, which just set
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// w_req_pending<=1 for this SAME w_req pulse
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// (real bug found via full regression, EXP-0048
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// /ERR-0023: without this the latch survives
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// uncontested, and next cycle w_eff_req reads
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// true from STALE w_req_pending/w_req_addr_lat,
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// issuing a bogus extra fetch that shifts every
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// subsequent response by one).
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w_rdata <= w_cache_data[w_hit_idx_c];
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w_ready <= 1'b1;
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w_cache_valid[w_hit_idx_c] <= 1'b0;
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w_req_pending <= 1'b0;
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end else if (w_eff_req) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b0;
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ctrl_addr <= w_eff_aligned_word_addr;
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ctrl_wmask <= 16'h0000;
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w_pending_upper_half <= w_eff_addr_is_upper_half;
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w_pending_addr <= w_eff_addr;
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w_req_pending <= 1'b0;
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state <= S_W_WAIT;
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end else if (ar_eff_req && !ar_eff_wr) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b0;
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ctrl_addr <= ar_eff_block_base;
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ctrl_wmask <= 16'h0000;
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ar_pending_word <= ar_eff_word_in_blk;
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ar_req_pending <= 1'b0;
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state <= S_AR_RD_WAIT;
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end else if (ar_eff_req && ar_eff_wr) begin
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// mask every word except the target one; within
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// the target word, pass ar_lb_n/ar_ub_n through
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// directly (same active-low "write this byte"
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// polarity as real SDRAM DQM: lb_n=0 -> DQM=0
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// -> byte written; lb_n=1 -> DQM=1 -> masked).
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b1;
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ctrl_addr <= ar_eff_block_base;
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ctrl_wdata <= {8{ar_eff_wdata}}; // replicate; only the target word's mask bits matter
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ctrl_wmask <= {16{1'b1}} & ~(16'h0003 << (ar_eff_word_in_blk*2)) | ({14'b0, ar_eff_ubn, ar_eff_lbn} << (ar_eff_word_in_blk*2));
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ar_req_pending <= 1'b0;
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state <= S_AR_WR_WAIT;
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end
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end
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S_W_WAIT: begin
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if (ctrl_ready) begin
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if (w_pending_upper_half) begin
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w_rdata <= ctrl_rdata[127:64];
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w_cache_data[w_alloc_ptr] <= ctrl_rdata[63:0];
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w_cache_addr[w_alloc_ptr] <= w_pending_addr - {{(ADDR_WIDTH-4){1'b0}}, 4'd8};
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end else begin
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w_rdata <= ctrl_rdata[63:0];
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w_cache_data[w_alloc_ptr] <= ctrl_rdata[127:64];
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w_cache_addr[w_alloc_ptr] <= w_pending_addr + {{(ADDR_WIDTH-4){1'b0}}, 4'd8};
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end
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w_cache_valid[w_alloc_ptr] <= 1'b1;
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w_alloc_ptr <= (w_alloc_ptr == W_ENTRIES[WEIDXW-1:0]-1'b1) ? {WEIDXW{1'b0}} : w_alloc_ptr + 1'b1;
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w_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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S_AR_RD_WAIT: begin
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if (ctrl_ready) begin
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ar_rdata <= ctrl_rdata[ar_pending_word*16 +: 16];
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ar_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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S_AR_WR_WAIT: begin
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if (ctrl_ready) begin
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ar_ready <= 1'b1;
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state <= S_IDLE;
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end
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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