micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
3226 lines
345 KiB
Plaintext
3226 lines
345 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Running command `
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read_verilog hardware/v2/rtl/neural_processor.v hardware/v2/rtl/neural_processor_array.v hardware/v2/synthesis/harness_neural_processor_array.v
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chparam -set N_PROCESSORS 8 harness_neural_processor_array
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synth_ecp5 -json hardware/v2/synthesis/harness_n8/top.json -top harness_neural_processor_array
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' --
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1. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor.v
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Parsing Verilog input from `hardware/v2/rtl/neural_processor.v' to AST representation.
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Generating RTLIL representation for module `\neural_processor'.
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Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193
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Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151
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Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122
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Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: hardware/v2/rtl/neural_processor_array.v
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Parsing Verilog input from `hardware/v2/rtl/neural_processor_array.v' to AST representation.
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Generating RTLIL representation for module `\neural_processor_array'.
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Successfully finished Verilog frontend.
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3. Executing Verilog-2005 frontend: hardware/v2/synthesis/harness_neural_processor_array.v
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Parsing Verilog input from `hardware/v2/synthesis/harness_neural_processor_array.v' to AST representation.
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Generating RTLIL representation for module `\harness_neural_processor_array'.
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Successfully finished Verilog frontend.
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Parameter \N_PROCESSORS = 8
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4. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_neural_processor_array'.
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Parameter \N_PROCESSORS = 8
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Generating RTLIL representation for module `$paramod\harness_neural_processor_array\N_PROCESSORS=s32'00000000000000000000000000001000'.
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5. Executing SYNTH_LATTICE pass.
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5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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5.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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5.3. Executing HIERARCHY pass (managing design hierarchy).
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5.3.1. Analyzing design hierarchy..
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Top module: \harness_neural_processor_array
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Used module: \neural_processor_array
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Used module: \neural_processor
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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5.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Warning: Replacing memory \tree with list of registers. See hardware/v2/rtl/neural_processor.v:193
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Warning: Replacing memory \prod1 with list of registers. See hardware/v2/rtl/neural_processor.v:151
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Warning: Replacing memory \w0 with list of registers. See hardware/v2/rtl/neural_processor.v:122
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Warning: Replacing memory \x0 with list of registers. See hardware/v2/rtl/neural_processor.v:121
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Reprocessing module neural_processor_array because instantiated module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor has become available.
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Generating RTLIL representation for module `\neural_processor_array'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Parameter \N_PROCESSORS = 8
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5.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\neural_processor_array'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Parameter \N_PROCESSORS = 8
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Generating RTLIL representation for module `$paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array'.
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5.3.4. Analyzing design hierarchy..
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Top module: \harness_neural_processor_array
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Used module: $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array
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Used module: \neural_processor
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \P_IN = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor'.
|
|
|
|
5.3.5. Analyzing design hierarchy..
|
|
Top module: \harness_neural_processor_array
|
|
Used module: $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array
|
|
Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor
|
|
|
|
5.3.6. Analyzing design hierarchy..
|
|
Top module: \harness_neural_processor_array
|
|
Used module: $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array
|
|
Used module: $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor
|
|
Removing unused module `\neural_processor_array'.
|
|
Removing unused module `\neural_processor'.
|
|
Removed 2 unused modules.
|
|
|
|
5.4. Executing PROC pass (convert processes to netlists).
|
|
|
|
5.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
5.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_processor_array.v:36$95 in module harness_neural_processor_array.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_neural_processor_array.v:119$100 in module harness_neural_processor_array.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$385 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$380 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:181$371 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:305$366 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:278$356 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:245$343 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:215$340 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:143$339 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Marked 2 switch rules as full_case in process $proc$hardware/v2/rtl/neural_processor.v:104$334 in module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Removed a total of 0 dead cases.
|
|
|
|
5.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 17 redundant assignments.
|
|
Promoted 25 assignments to connections.
|
|
|
|
5.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
5.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
5.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~20 debug messages>
|
|
|
|
5.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:36$95'.
|
|
1/1: $0\lfsr[31:0]
|
|
Creating decoders for process `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:119$100'.
|
|
1/1: $0\chk[7:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$411'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$410'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$409'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$408'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$407'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$406'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$405'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$404'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$402'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$400'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$398'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$396'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$394'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$392'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$390'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$388'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$386'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$385'.
|
|
1/2: $0\last_tree[2:2]
|
|
2/2: $0\valid_tree[2:2]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$383'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$381'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$380'.
|
|
1/2: $0\last_tree[1:1]
|
|
2/2: $0\valid_tree[1:1]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$378'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$376'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$374'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$372'.
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$371'.
|
|
1/2: $0\last_tree[0:0]
|
|
2/2: $0\valid_tree[0:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
1/8: $0\node_id_reg[15:0]
|
|
2/8: $0\activation_reg[1:0]
|
|
3/8: $0\bias_reg[7:0]
|
|
4/8: $0\np_error[0:0]
|
|
5/8: $0\np_state[3:0]
|
|
6/8: $0\result_node_id[15:0]
|
|
7/8: $0\result_data[7:0]
|
|
8/8: $0\result_valid[0:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$356'.
|
|
1/2: $0\valid7[0:0]
|
|
2/2: $0\y7[7:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
1/3: $0\last6[0:0]
|
|
2/3: $0\valid6[0:0]
|
|
3/3: $0\final_acc_reg[31:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
1/3: $0\last5[0:0]
|
|
2/3: $0\valid5[0:0]
|
|
3/3: $0\acc_reg[31:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
1/11: $0\last1[0:0]
|
|
2/11: $0\valid1[0:0]
|
|
3/11: $4\gi[31:0]
|
|
4/11: $0\prod1[7][31:0]
|
|
5/11: $0\prod1[6][31:0]
|
|
6/11: $0\prod1[5][31:0]
|
|
7/11: $0\prod1[4][31:0]
|
|
8/11: $0\prod1[3][31:0]
|
|
9/11: $0\prod1[2][31:0]
|
|
10/11: $0\prod1[1][31:0]
|
|
11/11: $0\prod1[0][31:0]
|
|
Creating decoders for process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
1/20: $2\gi[31:0]
|
|
2/20: $0\last0[0:0]
|
|
3/20: $0\valid0[0:0]
|
|
4/20: $1\gi[31:0]
|
|
5/20: $0\w0[7][7:0]
|
|
6/20: $0\w0[6][7:0]
|
|
7/20: $0\w0[5][7:0]
|
|
8/20: $0\w0[4][7:0]
|
|
9/20: $0\w0[3][7:0]
|
|
10/20: $0\w0[2][7:0]
|
|
11/20: $0\w0[1][7:0]
|
|
12/20: $0\w0[0][7:0]
|
|
13/20: $0\x0[7][7:0]
|
|
14/20: $0\x0[6][7:0]
|
|
15/20: $0\x0[5][7:0]
|
|
16/20: $0\x0[4][7:0]
|
|
17/20: $0\x0[3][7:0]
|
|
18/20: $0\x0[2][7:0]
|
|
19/20: $0\x0[1][7:0]
|
|
20/20: $0\x0[0][7:0]
|
|
|
|
5.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$411'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$410'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$409'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$408'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$407'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$406'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$405'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\level0[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$404'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[7]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$402'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[6]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$400'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[5]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$398'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[4]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$396'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[3]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$394'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[2]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$392'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[1]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$390'.
|
|
No latch inferred for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\product_comb[0]' from process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$388'.
|
|
|
|
5.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\harness_neural_processor_array.\lfsr' using process `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:36$95'.
|
|
created $dff cell `$procdff$904' with positive edge clock.
|
|
Creating register for signal `\harness_neural_processor_array.\chk' using process `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:119$100'.
|
|
created $dff cell `$procdff$905' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[16]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$386'.
|
|
created $dff cell `$procdff$906' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$385'.
|
|
created $dff cell `$procdff$907' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$385'.
|
|
created $dff cell `$procdff$908' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[9]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$383'.
|
|
created $dff cell `$procdff$909' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[8]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$381'.
|
|
created $dff cell `$procdff$910' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$380'.
|
|
created $dff cell `$procdff$911' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$380'.
|
|
created $dff cell `$procdff$912' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$378'.
|
|
created $dff cell `$procdff$913' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$376'.
|
|
created $dff cell `$procdff$914' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$374'.
|
|
created $dff cell `$procdff$915' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\tree[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$372'.
|
|
created $dff cell `$procdff$916' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$371'.
|
|
created $dff cell `$procdff$917' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last_tree [0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$371'.
|
|
created $dff cell `$procdff$918' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_valid' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$919' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_data' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$920' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\result_node_id' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$921' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_state' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$922' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\np_error' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$923' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\bias_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$924' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\activation_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$925' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\node_id_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
created $dff cell `$procdff$926' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$356'.
|
|
created $dff cell `$procdff$927' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\y7' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$356'.
|
|
created $dff cell `$procdff$928' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
created $dff cell `$procdff$929' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last6' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
created $dff cell `$procdff$930' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\final_acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
created $dff cell `$procdff$931' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\acc_reg' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
created $dff cell `$procdff$932' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
created $dff cell `$procdff$933' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last5' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
created $dff cell `$procdff$934' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$935' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$936' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last1' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$937' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$938' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$939' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$940' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$941' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$942' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$943' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$944' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\prod1[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
created $dff cell `$procdff$945' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\valid0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$946' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\last0' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$947' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$948' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$949' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$950' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$951' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$952' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$953' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$954' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$955' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\x0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$956' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[0]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$957' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[1]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$958' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[2]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$959' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[3]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$960' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[4]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$961' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[5]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$962' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[6]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$963' with positive edge clock.
|
|
Creating register for signal `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\w0[7]' using process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
created $dff cell `$procdff$964' with positive edge clock.
|
|
|
|
5.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
5.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:36$95'.
|
|
Removing empty process `harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:36$95'.
|
|
Found and cleaned up 1 empty switch in `\harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:119$100'.
|
|
Removing empty process `harness_neural_processor_array.$proc$hardware/v2/synthesis/harness_neural_processor_array.v:119$100'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$411'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$410'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$409'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$408'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$407'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$406'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$405'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:170$404'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$402'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$400'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$398'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$396'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$394'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$392'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$390'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:139$388'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$386'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$385'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$385'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$383'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:196$381'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$380'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$380'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$378'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$376'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$374'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:192$372'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$371'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:181$371'.
|
|
Found and cleaned up 6 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:305$366'.
|
|
Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$356'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:278$356'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:245$343'.
|
|
Found and cleaned up 3 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:215$340'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:143$339'.
|
|
Found and cleaned up 2 empty switches in `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
Removing empty process `$paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.$proc$hardware/v2/rtl/neural_processor.v:104$334'.
|
|
Cleaned up 20 empty switches.
|
|
|
|
5.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~1 debug messages>
|
|
Optimizing module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
<suppressed ~7 debug messages>
|
|
Optimizing module $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array.
|
|
|
|
5.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_processor_array...
|
|
Checking module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor...
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [31]:
|
|
port Q[31] of cell $procdff$948 ($dff)
|
|
port Q[31] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [30]:
|
|
port Q[30] of cell $procdff$948 ($dff)
|
|
port Q[30] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [29]:
|
|
port Q[29] of cell $procdff$948 ($dff)
|
|
port Q[29] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [28]:
|
|
port Q[28] of cell $procdff$948 ($dff)
|
|
port Q[28] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [27]:
|
|
port Q[27] of cell $procdff$948 ($dff)
|
|
port Q[27] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [26]:
|
|
port Q[26] of cell $procdff$948 ($dff)
|
|
port Q[26] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [25]:
|
|
port Q[25] of cell $procdff$948 ($dff)
|
|
port Q[25] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [24]:
|
|
port Q[24] of cell $procdff$948 ($dff)
|
|
port Q[24] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [23]:
|
|
port Q[23] of cell $procdff$948 ($dff)
|
|
port Q[23] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [22]:
|
|
port Q[22] of cell $procdff$948 ($dff)
|
|
port Q[22] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [21]:
|
|
port Q[21] of cell $procdff$948 ($dff)
|
|
port Q[21] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [20]:
|
|
port Q[20] of cell $procdff$948 ($dff)
|
|
port Q[20] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [19]:
|
|
port Q[19] of cell $procdff$948 ($dff)
|
|
port Q[19] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [18]:
|
|
port Q[18] of cell $procdff$948 ($dff)
|
|
port Q[18] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [17]:
|
|
port Q[17] of cell $procdff$948 ($dff)
|
|
port Q[17] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [16]:
|
|
port Q[16] of cell $procdff$948 ($dff)
|
|
port Q[16] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [15]:
|
|
port Q[15] of cell $procdff$948 ($dff)
|
|
port Q[15] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [14]:
|
|
port Q[14] of cell $procdff$948 ($dff)
|
|
port Q[14] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [13]:
|
|
port Q[13] of cell $procdff$948 ($dff)
|
|
port Q[13] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [12]:
|
|
port Q[12] of cell $procdff$948 ($dff)
|
|
port Q[12] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [11]:
|
|
port Q[11] of cell $procdff$948 ($dff)
|
|
port Q[11] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [10]:
|
|
port Q[10] of cell $procdff$948 ($dff)
|
|
port Q[10] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [9]:
|
|
port Q[9] of cell $procdff$948 ($dff)
|
|
port Q[9] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [8]:
|
|
port Q[8] of cell $procdff$948 ($dff)
|
|
port Q[8] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [7]:
|
|
port Q[7] of cell $procdff$948 ($dff)
|
|
port Q[7] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [6]:
|
|
port Q[6] of cell $procdff$948 ($dff)
|
|
port Q[6] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [5]:
|
|
port Q[5] of cell $procdff$948 ($dff)
|
|
port Q[5] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [4]:
|
|
port Q[4] of cell $procdff$948 ($dff)
|
|
port Q[4] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [3]:
|
|
port Q[3] of cell $procdff$948 ($dff)
|
|
port Q[3] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [2]:
|
|
port Q[2] of cell $procdff$948 ($dff)
|
|
port Q[2] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [1]:
|
|
port Q[1] of cell $procdff$948 ($dff)
|
|
port Q[1] of cell $procdff$935 ($dff)
|
|
Warning: multiple conflicting drivers for $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.\gi [0]:
|
|
port Q[0] of cell $procdff$948 ($dff)
|
|
port Q[0] of cell $procdff$935 ($dff)
|
|
Checking module $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array...
|
|
Found and reported 32 problems.
|
|
|
|
5.6. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$c0193c7ec190759e8025e35dead4531c56eb80a9\neural_processor.
|
|
Deleting now unused module $paramod$90391b607915058ca004f3099849c7f2a533f358\neural_processor_array.
|
|
<suppressed ~9 debug messages>
|
|
|
|
5.7. Executing TRIBUF pass.
|
|
|
|
5.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
5.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 48 unused cells and 1733 unused wires.
|
|
<suppressed ~193 debug messages>
|
|
|
|
5.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_processor_array...
|
|
Found and reported 0 problems.
|
|
|
|
5.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1671 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 1567 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
<suppressed ~312 debug messages>
|
|
Removed a total of 104 cells.
|
|
|
|
5.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1140 debug messages>
|
|
|
|
5.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1567 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 104 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1140 debug messages>
|
|
|
|
5.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1567 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.12.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
5.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[3].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[4].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[0].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[2].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[5].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[1].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[6].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Not marking harness_neural_processor_array.dut.GEN_NP[7].u_np.np_state as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
5.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
5.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
5.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
5.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
5.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
5.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
5.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1567 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1140 debug messages>
|
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5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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Optimizing cells in module \harness_neural_processor_array.
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Performed a total of 0 changes.
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5.14.5. Executing OPT_MERGE pass (detect identical cells).
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Finding identical cells in module `\harness_neural_processor_array'.
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Computing hashes of 1567 cells of `\harness_neural_processor_array'.
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Finding duplicate cells in `\harness_neural_processor_array'.
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Removed a total of 0 cells.
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5.14.6. Executing OPT_DFF pass (perform DFF optimizations).
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Adding SRST signal on $procdff$905 ($dff) from module harness_neural_processor_array (D = $xor$hardware/v2/synthesis/harness_neural_processor_array.v:121$107_Y, Q = \chk, rval = 8'00000000).
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Adding SRST signal on $procdff$904 ($dff) from module harness_neural_processor_array (D = { \lfsr [30:7] $xor$hardware/v2/synthesis/harness_neural_processor_array.v:38$99_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$699_Y, Q = \dut.GEN_NP[0].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$977 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.node_id_reg, Q = \dut.GEN_NP[0].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$674_Y, Q = \dut.GEN_NP[0].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$981 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$674_Y, Q = \dut.GEN_NP[0].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[0].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$665_Y, Q = \dut.GEN_NP[0].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$996 ($sdff) from module harness_neural_processor_array (D = \lfsr [8:1], Q = \dut.GEN_NP[0].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid_tree [1], Q = \dut.GEN_NP[7].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last_tree [1], Q = \dut.GEN_NP[7].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid_tree [0], Q = \dut.GEN_NP[7].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last_tree [0], Q = \dut.GEN_NP[7].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid1, Q = \dut.GEN_NP[7].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last1, Q = \dut.GEN_NP[7].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$720_Y, Q = \dut.GEN_NP[7].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1006 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$720_Y, Q = \dut.GEN_NP[7].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$710_Y, Q = \dut.GEN_NP[7].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1016 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.y7, Q = \dut.GEN_NP[7].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$699_Y, Q = \dut.GEN_NP[7].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1020 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.node_id_reg, Q = \dut.GEN_NP[7].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$674_Y, Q = \dut.GEN_NP[7].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1024 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$674_Y, Q = \dut.GEN_NP[7].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[7].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$665_Y, Q = \dut.GEN_NP[7].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1039 ($sdff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[7].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$651_Y, Q = \dut.GEN_NP[7].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1043 ($sdff) from module harness_neural_processor_array (D = \lfsr [9:8], Q = \dut.GEN_NP[7].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$637_Y, Q = \dut.GEN_NP[7].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1047 ($sdff) from module harness_neural_processor_array (D = \lfsr [23:8], Q = \dut.GEN_NP[7].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last6, Q = \dut.GEN_NP[7].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$732_Y, Q = \dut.GEN_NP[7].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid5, Q = \dut.GEN_NP[7].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last5, Q = \dut.GEN_NP[7].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[7].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$procmux$752_Y, Q = \dut.GEN_NP[7].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1056 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[7].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid_tree [2], Q = \dut.GEN_NP[7].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last_tree [2], Q = \dut.GEN_NP[7].u_np.last5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.valid0, Q = \dut.GEN_NP[7].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[7].u_np.last0, Q = \dut.GEN_NP[7].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] [15] \dut.GEN_NP[7].u_np.product_comb[0] }, Q = \dut.GEN_NP[7].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] [15] \dut.GEN_NP[7].u_np.product_comb[1] }, Q = \dut.GEN_NP[7].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] [15] \dut.GEN_NP[7].u_np.product_comb[2] }, Q = \dut.GEN_NP[7].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] [15] \dut.GEN_NP[7].u_np.product_comb[3] }, Q = \dut.GEN_NP[7].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] [15] \dut.GEN_NP[7].u_np.product_comb[4] }, Q = \dut.GEN_NP[7].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] [15] \dut.GEN_NP[7].u_np.product_comb[5] }, Q = \dut.GEN_NP[7].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] [15] \dut.GEN_NP[7].u_np.product_comb[6] }, Q = \dut.GEN_NP[7].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] [15] \dut.GEN_NP[7].u_np.product_comb[7] }, Q = \dut.GEN_NP[7].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[7].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[7].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [11], Q = \dut.GEN_NP[7].u_np.last0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[7].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[7].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[7].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[7].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[7].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[7].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[7].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[7].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[7].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[7].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[7].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [27:20], Q = \dut.GEN_NP[7].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [28:21], Q = \dut.GEN_NP[7].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [29:22], Q = \dut.GEN_NP[7].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [30:23], Q = \dut.GEN_NP[7].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[7].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [31:24], Q = \dut.GEN_NP[7].u_np.w0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[0].u_np.w0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[0].u_np.w0[6]).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid_tree [1], Q = \dut.GEN_NP[6].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last_tree [1], Q = \dut.GEN_NP[6].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid_tree [0], Q = \dut.GEN_NP[6].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last_tree [0], Q = \dut.GEN_NP[6].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid1, Q = \dut.GEN_NP[6].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last1, Q = \dut.GEN_NP[6].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$720_Y, Q = \dut.GEN_NP[6].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1174 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$720_Y, Q = \dut.GEN_NP[6].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$710_Y, Q = \dut.GEN_NP[6].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1184 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.y7, Q = \dut.GEN_NP[6].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$699_Y, Q = \dut.GEN_NP[6].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1188 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.node_id_reg, Q = \dut.GEN_NP[6].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$674_Y, Q = \dut.GEN_NP[6].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1192 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$674_Y, Q = \dut.GEN_NP[6].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[6].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$665_Y, Q = \dut.GEN_NP[6].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1207 ($sdff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[6].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$651_Y, Q = \dut.GEN_NP[6].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1211 ($sdff) from module harness_neural_processor_array (D = \lfsr [8:7], Q = \dut.GEN_NP[6].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$637_Y, Q = \dut.GEN_NP[6].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1215 ($sdff) from module harness_neural_processor_array (D = \lfsr [22:7], Q = \dut.GEN_NP[6].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last6, Q = \dut.GEN_NP[6].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$732_Y, Q = \dut.GEN_NP[6].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid5, Q = \dut.GEN_NP[6].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last5, Q = \dut.GEN_NP[6].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[6].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$procmux$752_Y, Q = \dut.GEN_NP[6].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1224 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[6].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid_tree [2], Q = \dut.GEN_NP[6].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last_tree [2], Q = \dut.GEN_NP[6].u_np.last5, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[0].u_np.w0[5]).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.valid0, Q = \dut.GEN_NP[6].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[6].u_np.last0, Q = \dut.GEN_NP[6].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] [15] \dut.GEN_NP[6].u_np.product_comb[0] }, Q = \dut.GEN_NP[6].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] [15] \dut.GEN_NP[6].u_np.product_comb[1] }, Q = \dut.GEN_NP[6].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] [15] \dut.GEN_NP[6].u_np.product_comb[2] }, Q = \dut.GEN_NP[6].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] [15] \dut.GEN_NP[6].u_np.product_comb[3] }, Q = \dut.GEN_NP[6].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] [15] \dut.GEN_NP[6].u_np.product_comb[4] }, Q = \dut.GEN_NP[6].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] [15] \dut.GEN_NP[6].u_np.product_comb[5] }, Q = \dut.GEN_NP[6].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] [15] \dut.GEN_NP[6].u_np.product_comb[6] }, Q = \dut.GEN_NP[6].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] [15] \dut.GEN_NP[6].u_np.product_comb[7] }, Q = \dut.GEN_NP[6].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[6].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[6].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [10], Q = \dut.GEN_NP[6].u_np.last0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[0].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[6].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[6].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[6].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[6].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[6].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[6].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[6].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[6].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[6].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[6].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[6].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[6].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [27:20], Q = \dut.GEN_NP[6].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [28:21], Q = \dut.GEN_NP[6].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [29:22], Q = \dut.GEN_NP[6].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[6].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [30:23], Q = \dut.GEN_NP[6].u_np.w0[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last5, Q = \dut.GEN_NP[0].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[0].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[0].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[0].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[0].u_np.w0[0]).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid_tree [1], Q = \dut.GEN_NP[5].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last_tree [1], Q = \dut.GEN_NP[5].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid_tree [0], Q = \dut.GEN_NP[5].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last_tree [0], Q = \dut.GEN_NP[5].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid1, Q = \dut.GEN_NP[5].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last1, Q = \dut.GEN_NP[5].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$720_Y, Q = \dut.GEN_NP[5].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1363 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$720_Y, Q = \dut.GEN_NP[5].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$710_Y, Q = \dut.GEN_NP[5].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1373 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.y7, Q = \dut.GEN_NP[5].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$699_Y, Q = \dut.GEN_NP[5].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1377 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.node_id_reg, Q = \dut.GEN_NP[5].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$674_Y, Q = \dut.GEN_NP[5].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1381 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$674_Y, Q = \dut.GEN_NP[5].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[5].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$665_Y, Q = \dut.GEN_NP[5].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1396 ($sdff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[5].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$651_Y, Q = \dut.GEN_NP[5].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1400 ($sdff) from module harness_neural_processor_array (D = \lfsr [7:6], Q = \dut.GEN_NP[5].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$637_Y, Q = \dut.GEN_NP[5].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1404 ($sdff) from module harness_neural_processor_array (D = \lfsr [21:6], Q = \dut.GEN_NP[5].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last6, Q = \dut.GEN_NP[5].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$732_Y, Q = \dut.GEN_NP[5].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid5, Q = \dut.GEN_NP[5].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last5, Q = \dut.GEN_NP[5].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[5].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$procmux$752_Y, Q = \dut.GEN_NP[5].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1413 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[5].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid_tree [2], Q = \dut.GEN_NP[5].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last_tree [2], Q = \dut.GEN_NP[5].u_np.last5, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[0].u_np.x0[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.valid0, Q = \dut.GEN_NP[5].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[5].u_np.last0, Q = \dut.GEN_NP[5].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] [15] \dut.GEN_NP[5].u_np.product_comb[0] }, Q = \dut.GEN_NP[5].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] [15] \dut.GEN_NP[5].u_np.product_comb[1] }, Q = \dut.GEN_NP[5].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] [15] \dut.GEN_NP[5].u_np.product_comb[2] }, Q = \dut.GEN_NP[5].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] [15] \dut.GEN_NP[5].u_np.product_comb[3] }, Q = \dut.GEN_NP[5].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] [15] \dut.GEN_NP[5].u_np.product_comb[4] }, Q = \dut.GEN_NP[5].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] [15] \dut.GEN_NP[5].u_np.product_comb[5] }, Q = \dut.GEN_NP[5].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] [15] \dut.GEN_NP[5].u_np.product_comb[6] }, Q = \dut.GEN_NP[5].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] [15] \dut.GEN_NP[5].u_np.product_comb[7] }, Q = \dut.GEN_NP[5].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[5].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[5].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [9], Q = \dut.GEN_NP[5].u_np.last0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[0].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[5].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[5].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[5].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[5].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[5].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[5].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[5].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[5].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[5].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[5].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[5].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[5].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[5].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [27:20], Q = \dut.GEN_NP[5].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [28:21], Q = \dut.GEN_NP[5].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[5].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [29:22], Q = \dut.GEN_NP[5].u_np.w0[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid5, Q = \dut.GEN_NP[0].u_np.valid6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$732_Y, Q = \dut.GEN_NP[0].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last6, Q = \dut.GEN_NP[0].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[0].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[0].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [12:5], Q = \dut.GEN_NP[0].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [11:4], Q = \dut.GEN_NP[0].u_np.x0[2]).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid_tree [1], Q = \dut.GEN_NP[4].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last_tree [1], Q = \dut.GEN_NP[4].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid_tree [0], Q = \dut.GEN_NP[4].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last_tree [0], Q = \dut.GEN_NP[4].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid1, Q = \dut.GEN_NP[4].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last1, Q = \dut.GEN_NP[4].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$720_Y, Q = \dut.GEN_NP[4].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1554 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$720_Y, Q = \dut.GEN_NP[4].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$710_Y, Q = \dut.GEN_NP[4].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1564 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.y7, Q = \dut.GEN_NP[4].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$699_Y, Q = \dut.GEN_NP[4].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1568 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.node_id_reg, Q = \dut.GEN_NP[4].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$674_Y, Q = \dut.GEN_NP[4].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1572 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$674_Y, Q = \dut.GEN_NP[4].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[4].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$665_Y, Q = \dut.GEN_NP[4].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1587 ($sdff) from module harness_neural_processor_array (D = \lfsr [12:5], Q = \dut.GEN_NP[4].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$651_Y, Q = \dut.GEN_NP[4].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1591 ($sdff) from module harness_neural_processor_array (D = \lfsr [6:5], Q = \dut.GEN_NP[4].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$637_Y, Q = \dut.GEN_NP[4].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1595 ($sdff) from module harness_neural_processor_array (D = \lfsr [20:5], Q = \dut.GEN_NP[4].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last6, Q = \dut.GEN_NP[4].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$732_Y, Q = \dut.GEN_NP[4].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid5, Q = \dut.GEN_NP[4].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last5, Q = \dut.GEN_NP[4].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[4].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$procmux$752_Y, Q = \dut.GEN_NP[4].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1604 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[4].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid_tree [2], Q = \dut.GEN_NP[4].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last_tree [2], Q = \dut.GEN_NP[4].u_np.last5, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [10:3], Q = \dut.GEN_NP[0].u_np.x0[1]).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.valid0, Q = \dut.GEN_NP[4].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[4].u_np.last0, Q = \dut.GEN_NP[4].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] [15] \dut.GEN_NP[4].u_np.product_comb[0] }, Q = \dut.GEN_NP[4].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] [15] \dut.GEN_NP[4].u_np.product_comb[1] }, Q = \dut.GEN_NP[4].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] [15] \dut.GEN_NP[4].u_np.product_comb[2] }, Q = \dut.GEN_NP[4].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] [15] \dut.GEN_NP[4].u_np.product_comb[3] }, Q = \dut.GEN_NP[4].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] [15] \dut.GEN_NP[4].u_np.product_comb[4] }, Q = \dut.GEN_NP[4].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] [15] \dut.GEN_NP[4].u_np.product_comb[5] }, Q = \dut.GEN_NP[4].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] [15] \dut.GEN_NP[4].u_np.product_comb[6] }, Q = \dut.GEN_NP[4].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] [15] \dut.GEN_NP[4].u_np.product_comb[7] }, Q = \dut.GEN_NP[4].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[4].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[4].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [8], Q = \dut.GEN_NP[4].u_np.last0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [9:2], Q = \dut.GEN_NP[0].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[4].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[4].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[4].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[4].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[4].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[4].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[4].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[4].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[4].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[4].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[4].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[4].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[4].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[4].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [27:20], Q = \dut.GEN_NP[4].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[4].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [28:21], Q = \dut.GEN_NP[4].u_np.w0[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$651_Y, Q = \dut.GEN_NP[0].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1716 ($sdff) from module harness_neural_processor_array (D = \lfsr [2:1], Q = \dut.GEN_NP[0].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [4], Q = \dut.GEN_NP[0].u_np.last0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[0].u_np.valid0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] [15] \dut.GEN_NP[0].u_np.product_comb[7] }, Q = \dut.GEN_NP[0].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid_tree [1], Q = \dut.GEN_NP[3].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last_tree [1], Q = \dut.GEN_NP[3].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid_tree [0], Q = \dut.GEN_NP[3].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last_tree [0], Q = \dut.GEN_NP[3].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid1, Q = \dut.GEN_NP[3].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last1, Q = \dut.GEN_NP[3].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$720_Y, Q = \dut.GEN_NP[3].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1733 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$720_Y, Q = \dut.GEN_NP[3].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$710_Y, Q = \dut.GEN_NP[3].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1743 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.y7, Q = \dut.GEN_NP[3].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$699_Y, Q = \dut.GEN_NP[3].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1747 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.node_id_reg, Q = \dut.GEN_NP[3].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$674_Y, Q = \dut.GEN_NP[3].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1751 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$674_Y, Q = \dut.GEN_NP[3].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[3].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$665_Y, Q = \dut.GEN_NP[3].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1766 ($sdff) from module harness_neural_processor_array (D = \lfsr [11:4], Q = \dut.GEN_NP[3].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$651_Y, Q = \dut.GEN_NP[3].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1770 ($sdff) from module harness_neural_processor_array (D = \lfsr [5:4], Q = \dut.GEN_NP[3].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$637_Y, Q = \dut.GEN_NP[3].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1774 ($sdff) from module harness_neural_processor_array (D = \lfsr [19:4], Q = \dut.GEN_NP[3].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last6, Q = \dut.GEN_NP[3].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$732_Y, Q = \dut.GEN_NP[3].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid5, Q = \dut.GEN_NP[3].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last5, Q = \dut.GEN_NP[3].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[3].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$procmux$752_Y, Q = \dut.GEN_NP[3].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1783 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[3].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid_tree [2], Q = \dut.GEN_NP[3].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last_tree [2], Q = \dut.GEN_NP[3].u_np.last5, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] [15] \dut.GEN_NP[0].u_np.product_comb[6] }, Q = \dut.GEN_NP[0].u_np.prod1[6]).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.valid0, Q = \dut.GEN_NP[3].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[3].u_np.last0, Q = \dut.GEN_NP[3].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] [15] \dut.GEN_NP[3].u_np.product_comb[0] }, Q = \dut.GEN_NP[3].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] [15] \dut.GEN_NP[3].u_np.product_comb[1] }, Q = \dut.GEN_NP[3].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] [15] \dut.GEN_NP[3].u_np.product_comb[2] }, Q = \dut.GEN_NP[3].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] [15] \dut.GEN_NP[3].u_np.product_comb[3] }, Q = \dut.GEN_NP[3].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] [15] \dut.GEN_NP[3].u_np.product_comb[4] }, Q = \dut.GEN_NP[3].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] [15] \dut.GEN_NP[3].u_np.product_comb[5] }, Q = \dut.GEN_NP[3].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] [15] \dut.GEN_NP[3].u_np.product_comb[6] }, Q = \dut.GEN_NP[3].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] [15] \dut.GEN_NP[3].u_np.product_comb[7] }, Q = \dut.GEN_NP[3].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[3].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[3].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [7], Q = \dut.GEN_NP[3].u_np.last0, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] [15] \dut.GEN_NP[0].u_np.product_comb[5] }, Q = \dut.GEN_NP[0].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [12:5], Q = \dut.GEN_NP[3].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[3].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[3].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[3].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[3].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[3].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[3].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[3].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[3].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[3].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[3].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[3].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[3].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[3].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[3].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[3].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [27:20], Q = \dut.GEN_NP[3].u_np.w0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] [15] \dut.GEN_NP[0].u_np.product_comb[4] }, Q = \dut.GEN_NP[0].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] [15] \dut.GEN_NP[0].u_np.product_comb[3] }, Q = \dut.GEN_NP[0].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] [15] \dut.GEN_NP[0].u_np.product_comb[2] }, Q = \dut.GEN_NP[0].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] [15] \dut.GEN_NP[0].u_np.product_comb[1] }, Q = \dut.GEN_NP[0].u_np.prod1[1]).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid_tree [1], Q = \dut.GEN_NP[2].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last_tree [1], Q = \dut.GEN_NP[2].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid_tree [0], Q = \dut.GEN_NP[2].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last_tree [0], Q = \dut.GEN_NP[2].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid1, Q = \dut.GEN_NP[2].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last1, Q = \dut.GEN_NP[2].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$720_Y, Q = \dut.GEN_NP[2].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$1897 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$720_Y, Q = \dut.GEN_NP[2].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$710_Y, Q = \dut.GEN_NP[2].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1907 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.y7, Q = \dut.GEN_NP[2].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$699_Y, Q = \dut.GEN_NP[2].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1911 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.node_id_reg, Q = \dut.GEN_NP[2].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$674_Y, Q = \dut.GEN_NP[2].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$1915 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$674_Y, Q = \dut.GEN_NP[2].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[2].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$665_Y, Q = \dut.GEN_NP[2].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$1930 ($sdff) from module harness_neural_processor_array (D = \lfsr [10:3], Q = \dut.GEN_NP[2].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$651_Y, Q = \dut.GEN_NP[2].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$1934 ($sdff) from module harness_neural_processor_array (D = \lfsr [4:3], Q = \dut.GEN_NP[2].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$637_Y, Q = \dut.GEN_NP[2].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$1938 ($sdff) from module harness_neural_processor_array (D = \lfsr [18:3], Q = \dut.GEN_NP[2].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last6, Q = \dut.GEN_NP[2].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$732_Y, Q = \dut.GEN_NP[2].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid5, Q = \dut.GEN_NP[2].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last5, Q = \dut.GEN_NP[2].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[2].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$procmux$752_Y, Q = \dut.GEN_NP[2].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$1947 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[2].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid_tree [2], Q = \dut.GEN_NP[2].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last_tree [2], Q = \dut.GEN_NP[2].u_np.last5, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] [15] \dut.GEN_NP[0].u_np.product_comb[0] }, Q = \dut.GEN_NP[0].u_np.prod1[0]).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.valid0, Q = \dut.GEN_NP[2].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[2].u_np.last0, Q = \dut.GEN_NP[2].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] [15] \dut.GEN_NP[2].u_np.product_comb[0] }, Q = \dut.GEN_NP[2].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] [15] \dut.GEN_NP[2].u_np.product_comb[1] }, Q = \dut.GEN_NP[2].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] [15] \dut.GEN_NP[2].u_np.product_comb[2] }, Q = \dut.GEN_NP[2].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] [15] \dut.GEN_NP[2].u_np.product_comb[3] }, Q = \dut.GEN_NP[2].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] [15] \dut.GEN_NP[2].u_np.product_comb[4] }, Q = \dut.GEN_NP[2].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] [15] \dut.GEN_NP[2].u_np.product_comb[5] }, Q = \dut.GEN_NP[2].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] [15] \dut.GEN_NP[2].u_np.product_comb[6] }, Q = \dut.GEN_NP[2].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] [15] \dut.GEN_NP[2].u_np.product_comb[7] }, Q = \dut.GEN_NP[2].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[2].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[2].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [6], Q = \dut.GEN_NP[2].u_np.last0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last0, Q = \dut.GEN_NP[0].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [11:4], Q = \dut.GEN_NP[2].u_np.x0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [12:5], Q = \dut.GEN_NP[2].u_np.x0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[2].u_np.x0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[2].u_np.x0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[2].u_np.x0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[2].u_np.x0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[2].u_np.x0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[2].u_np.x0[7]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[2].u_np.w0[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[2].u_np.w0[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[2].u_np.w0[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[2].u_np.w0[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[2].u_np.w0[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[2].u_np.w0[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[2].u_np.w0[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[2].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [26:19], Q = \dut.GEN_NP[2].u_np.w0[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid_tree [1], Q = \dut.GEN_NP[0].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last_tree [1], Q = \dut.GEN_NP[0].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid_tree [0], Q = \dut.GEN_NP[0].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last_tree [0], Q = \dut.GEN_NP[0].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid0, Q = \dut.GEN_NP[0].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$637_Y, Q = \dut.GEN_NP[0].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$2056 ($sdff) from module harness_neural_processor_array (D = \lfsr [16:1], Q = \dut.GEN_NP[0].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last_tree [2], Q = \dut.GEN_NP[0].u_np.last5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid_tree [2], Q = \dut.GEN_NP[0].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$907 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid_tree [1], Q = \dut.GEN_NP[1].u_np.valid_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$908 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last_tree [1], Q = \dut.GEN_NP[1].u_np.last_tree [2], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$911 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid_tree [0], Q = \dut.GEN_NP[1].u_np.valid_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$912 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last_tree [0], Q = \dut.GEN_NP[1].u_np.last_tree [1], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid1, Q = \dut.GEN_NP[1].u_np.valid_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last1, Q = \dut.GEN_NP[1].u_np.last_tree [0], rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$720_Y, Q = \dut.GEN_NP[1].u_np.result_valid, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$2068 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$720_Y, Q = \dut.GEN_NP[1].u_np.result_valid).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$710_Y, Q = \dut.GEN_NP[1].u_np.result_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$2078 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.y7, Q = \dut.GEN_NP[1].u_np.result_data).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$921 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$699_Y, Q = \dut.GEN_NP[1].u_np.result_node_id, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$2082 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.node_id_reg, Q = \dut.GEN_NP[1].u_np.result_node_id).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$922 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$674_Y, Q = \dut.GEN_NP[1].u_np.np_state, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$2086 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$674_Y, Q = \dut.GEN_NP[1].u_np.np_state).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$923 ($dff) from module harness_neural_processor_array (D = 1'0, Q = \dut.GEN_NP[1].u_np.np_error).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$924 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$665_Y, Q = \dut.GEN_NP[1].u_np.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$2101 ($sdff) from module harness_neural_processor_array (D = \lfsr [9:2], Q = \dut.GEN_NP[1].u_np.bias_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$925 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$651_Y, Q = \dut.GEN_NP[1].u_np.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$2105 ($sdff) from module harness_neural_processor_array (D = \lfsr [3:2], Q = \dut.GEN_NP[1].u_np.activation_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$926 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$637_Y, Q = \dut.GEN_NP[1].u_np.node_id_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$2109 ($sdff) from module harness_neural_processor_array (D = \lfsr [17:2], Q = \dut.GEN_NP[1].u_np.node_id_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$927 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last6, Q = \dut.GEN_NP[1].u_np.valid7, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$928 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$732_Y, Q = \dut.GEN_NP[1].u_np.y7).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$929 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid5, Q = \dut.GEN_NP[1].u_np.valid6, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$930 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last5, Q = \dut.GEN_NP[1].u_np.last6, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[1].u_np.final_acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$procmux$752_Y, Q = \dut.GEN_NP[1].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$2118 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[1].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$933 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid_tree [2], Q = \dut.GEN_NP[1].u_np.valid5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$934 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last_tree [2], Q = \dut.GEN_NP[1].u_np.last5, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$932 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$752_Y, Q = \dut.GEN_NP[0].u_np.acc_reg, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$2124 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342_Y, Q = \dut.GEN_NP[0].u_np.acc_reg).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$936 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.valid0, Q = \dut.GEN_NP[1].u_np.valid1, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$937 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[1].u_np.last0, Q = \dut.GEN_NP[1].u_np.last1, rval = 1'0).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$938 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] [15] \dut.GEN_NP[1].u_np.product_comb[0] }, Q = \dut.GEN_NP[1].u_np.prod1[0]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$939 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] [15] \dut.GEN_NP[1].u_np.product_comb[1] }, Q = \dut.GEN_NP[1].u_np.prod1[1]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$940 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] [15] \dut.GEN_NP[1].u_np.product_comb[2] }, Q = \dut.GEN_NP[1].u_np.prod1[2]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$941 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] [15] \dut.GEN_NP[1].u_np.product_comb[3] }, Q = \dut.GEN_NP[1].u_np.prod1[3]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$942 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] [15] \dut.GEN_NP[1].u_np.product_comb[4] }, Q = \dut.GEN_NP[1].u_np.prod1[4]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$943 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] [15] \dut.GEN_NP[1].u_np.product_comb[5] }, Q = \dut.GEN_NP[1].u_np.prod1[5]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$944 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] [15] \dut.GEN_NP[1].u_np.product_comb[6] }, Q = \dut.GEN_NP[1].u_np.prod1[6]).
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Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$945 ($dff) from module harness_neural_processor_array (D = { \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] [15] \dut.GEN_NP[1].u_np.product_comb[7] }, Q = \dut.GEN_NP[1].u_np.prod1[7]).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$946 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[1].u_np.$logic_and$hardware/v2/rtl/neural_processor.v:109$335_Y, Q = \dut.GEN_NP[1].u_np.valid0, rval = 1'0).
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Adding SRST signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$947 ($dff) from module harness_neural_processor_array (D = \lfsr [5], Q = \dut.GEN_NP[1].u_np.last0, rval = 1'0).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$931 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344_Y, Q = \dut.GEN_NP[0].u_np.final_acc_reg).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$949 ($dff) from module harness_neural_processor_array (D = \lfsr [10:3], Q = \dut.GEN_NP[1].u_np.x0[0]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$950 ($dff) from module harness_neural_processor_array (D = \lfsr [11:4], Q = \dut.GEN_NP[1].u_np.x0[1]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$951 ($dff) from module harness_neural_processor_array (D = \lfsr [12:5], Q = \dut.GEN_NP[1].u_np.x0[2]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$952 ($dff) from module harness_neural_processor_array (D = \lfsr [13:6], Q = \dut.GEN_NP[1].u_np.x0[3]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$953 ($dff) from module harness_neural_processor_array (D = \lfsr [14:7], Q = \dut.GEN_NP[1].u_np.x0[4]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$954 ($dff) from module harness_neural_processor_array (D = \lfsr [15:8], Q = \dut.GEN_NP[1].u_np.x0[5]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$955 ($dff) from module harness_neural_processor_array (D = \lfsr [16:9], Q = \dut.GEN_NP[1].u_np.x0[6]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$956 ($dff) from module harness_neural_processor_array (D = \lfsr [17:10], Q = \dut.GEN_NP[1].u_np.x0[7]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$957 ($dff) from module harness_neural_processor_array (D = \lfsr [18:11], Q = \dut.GEN_NP[1].u_np.w0[0]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$958 ($dff) from module harness_neural_processor_array (D = \lfsr [19:12], Q = \dut.GEN_NP[1].u_np.w0[1]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$959 ($dff) from module harness_neural_processor_array (D = \lfsr [20:13], Q = \dut.GEN_NP[1].u_np.w0[2]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$960 ($dff) from module harness_neural_processor_array (D = \lfsr [21:14], Q = \dut.GEN_NP[1].u_np.w0[3]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$961 ($dff) from module harness_neural_processor_array (D = \lfsr [22:15], Q = \dut.GEN_NP[1].u_np.w0[4]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$962 ($dff) from module harness_neural_processor_array (D = \lfsr [23:16], Q = \dut.GEN_NP[1].u_np.w0[5]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$963 ($dff) from module harness_neural_processor_array (D = \lfsr [24:17], Q = \dut.GEN_NP[1].u_np.w0[6]).
|
|
Adding EN signal on $flatten\dut.\GEN_NP[1].u_np.$procdff$964 ($dff) from module harness_neural_processor_array (D = \lfsr [25:18], Q = \dut.GEN_NP[1].u_np.w0[7]).
|
|
Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$917 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.valid1, Q = \dut.GEN_NP[0].u_np.valid_tree [0], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$918 ($dff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.last1, Q = \dut.GEN_NP[0].u_np.last_tree [0], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$919 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$720_Y, Q = \dut.GEN_NP[0].u_np.result_valid, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$2227 ($sdff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$720_Y, Q = \dut.GEN_NP[0].u_np.result_valid).
|
|
Adding SRST signal on $flatten\dut.\GEN_NP[0].u_np.$procdff$920 ($dff) from module harness_neural_processor_array (D = $flatten\dut.\GEN_NP[0].u_np.$procmux$710_Y, Q = \dut.GEN_NP[0].u_np.result_data, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$2237 ($sdff) from module harness_neural_processor_array (D = \dut.GEN_NP[0].u_np.y7, Q = \dut.GEN_NP[0].u_np.result_data).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$2100 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1929 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1765 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1586 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1395 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1206 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1038 ($dffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$995 ($dffe) from module harness_neural_processor_array.
|
|
|
|
5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 633 unused cells and 633 unused wires.
|
|
<suppressed ~634 debug messages>
|
|
|
|
5.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~17 debug messages>
|
|
|
|
5.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~130 debug messages>
|
|
|
|
5.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1326 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 1159 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 1039 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
<suppressed ~861 debug messages>
|
|
Removed a total of 287 cells.
|
|
|
|
5.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 288 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.14.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~130 debug messages>
|
|
|
|
5.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.14.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1039 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.14.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.14.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.14.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2238 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2137 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2136 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2135 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2134 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2133 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2132 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2131 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2130 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$2093 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$2089 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2083 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2079 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1963 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1962 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1961 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1960 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1959 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1958 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1957 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1956 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1953 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1922 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1918 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1912 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1908 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1890 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1889 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1888 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1887 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1806 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1799 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1798 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1797 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1796 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1795 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1794 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1793 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1792 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1789 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1758 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1754 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1748 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1744 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1726 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1624 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1623 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1622 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1621 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1620 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1619 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1618 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1617 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1579 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1575 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1569 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1565 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1526 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1433 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1432 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1431 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1430 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1429 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1428 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1427 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1426 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1388 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1384 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1378 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1374 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1244 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1243 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1242 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1241 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1240 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1239 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1238 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1237 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1199 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1195 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1189 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1185 ($sdffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1071 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1070 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1069 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1068 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1067 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1066 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1065 ($dffe).
|
|
Removed top 16 bits (of 32) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1064 ($dffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1031 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$1027 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1021 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1017 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$988 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell harness_neural_processor_array.$auto$opt_dff.cc:320:make_patterns_logic$984 ($ne).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$978 ($sdffe).
|
|
Removed top 24 bits (of 32) from mux cell harness_neural_processor_array.$procmux$605 ($mux).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procdff$916 ($dff).
|
|
Removed top 24 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$675_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$676_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$685_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$686_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$721_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$724_CMP0 ($eq).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$732 ($mux).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procdff$913 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procdff$914 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procdff$915 ($dff).
|
|
Removed top 15 bits (of 32) from FF cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procdff$916 ($dff).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$eq$hardware/v2/rtl/neural_processor.v:93$333 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$eq$hardware/v2/rtl/neural_processor.v:93$333 ($eq).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2114 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2110 ($sdffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$2057 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1943 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1939 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1779 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1775 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1600 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1596 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1409 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1405 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1220 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1216 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1052 ($dffe).
|
|
Removed top 15 bits (of 16) from FF cell harness_neural_processor_array.$auto$ff.cc:337:slice$1048 ($sdffe).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
Converting cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add) from unsigned to signed.
|
|
Removed top 15 bits (of 32) from port A of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 15 bits (of 32) from port B of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 14 bits (of 32) from port Y of cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$732 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:263$353 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:268$355 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352 ($mux).
|
|
Removed top 7 bits (of 8) from mux cell harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354 ($mux).
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[5].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[0].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[6].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[2].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[3].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[1].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:269$354_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[7].u_np.$ternary$hardware/v2/rtl/neural_processor.v:264$352_Y.
|
|
Removed top 7 bits (of 8) from wire harness_neural_processor_array.$flatten\dut.\GEN_NP[4].u_np.$procmux$732_Y.
|
|
Removed top 7 bits (of 64) from wire harness_neural_processor_array.result_data.
|
|
Removed top 15 bits (of 128) from wire harness_neural_processor_array.result_node_id.
|
|
Removed top 24 bits (of 32) from wire harness_neural_processor_array.$0\lfsr[31:0].
|
|
|
|
5.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 27 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
5.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.19.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
5.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.22.2. Continuing TECHMAP pass.
|
|
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
|
|
No more expansions possible.
|
|
<suppressed ~148 debug messages>
|
|
|
|
5.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.23.2. Continuing TECHMAP pass.
|
|
Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~86 debug messages>
|
|
|
|
5.24. Executing ALUMACC pass (create $alu and $macc cells).
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Extracting $alu and $macc cells in module harness_neural_processor_array:
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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|
creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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|
creating $macc model for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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|
creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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|
creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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|
creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
|
|
creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
|
|
creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
|
creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
|
|
creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
|
|
creating $macc model for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379 ($add).
|
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344 ($add).
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creating $macc model for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342 ($add).
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
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creating $alu model for $macc $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
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creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384.
|
|
creating $alu model for $macc $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387.
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2397
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2400
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2403
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2406
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2409
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2412
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2415
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2418
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2421
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2424
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2427
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2430
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2433
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2436
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2439
|
|
creating $alu cell for $flatten\dut.\GEN_NP[3].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2442
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2445
|
|
creating $alu cell for $flatten\dut.\GEN_NP[1].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2448
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2451
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2454
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2457
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2460
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2463
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2466
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2469
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2472
|
|
creating $alu cell for $flatten\dut.\GEN_NP[4].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2475
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2478
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2481
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2484
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2487
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2490
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2493
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2496
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2499
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2502
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2505
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2508
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2511
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2514
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2517
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2520
|
|
creating $alu cell for $flatten\dut.\GEN_NP[5].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2523
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2526
|
|
creating $alu cell for $flatten\dut.\GEN_NP[2].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2529
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2532
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2535
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2538
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2541
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2544
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2547
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2550
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2553
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2556
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2559
|
|
creating $alu cell for $flatten\dut.\GEN_NP[6].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2562
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2565
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2568
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2571
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2574
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2577
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2580
|
|
creating $alu cell for $flatten\dut.\GEN_NP[0].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2583
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$387: $auto$alumacc.cc:548:replace_alu$2586
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$384: $auto$alumacc.cc:548:replace_alu$2589
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:197$382: $auto$alumacc.cc:548:replace_alu$2592
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$379: $auto$alumacc.cc:548:replace_alu$2595
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$377: $auto$alumacc.cc:548:replace_alu$2598
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$375: $auto$alumacc.cc:548:replace_alu$2601
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:193$373: $auto$alumacc.cc:548:replace_alu$2604
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:252$344: $auto$alumacc.cc:548:replace_alu$2607
|
|
creating $alu cell for $flatten\dut.\GEN_NP[7].u_np.$add$hardware/v2/rtl/neural_processor.v:226$342: $auto$alumacc.cc:548:replace_alu$2610
|
|
created 72 $alu and 0 $macc cells.
|
|
|
|
5.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1039 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~130 debug messages>
|
|
|
|
5.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1039 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 512 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.25.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~130 debug messages>
|
|
|
|
5.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.25.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 1039 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.25.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.25.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.25.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.26. Executing MEMORY pass.
|
|
|
|
5.26.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
5.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
5.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
|
|
5.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
5.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
|
|
5.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
5.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
5.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
5.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
|
|
5.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.29.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
5.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~362 debug messages>
|
|
|
|
5.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 991 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 48 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.30.5. Finished fast OPT passes.
|
|
|
|
5.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
5.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 991 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~82 debug messages>
|
|
|
|
5.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[0].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[0].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[0].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[0].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[3].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[3].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[3].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[3].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[1].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[1].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[1].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[1].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[2].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[2].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[2].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[2].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[4].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[4].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[4].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[4].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[5].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[5].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[5].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[5].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[6].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[6].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[6].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[6].u_np.$procmux$674_Y [3] = 1'0
|
|
Consolidated identical input bits for $pmux cell $flatten\dut.\GEN_NP[7].u_np.$procmux$674:
|
|
Old ports: A=4'0110, B=24'000100100011010001010000, Y=$flatten\dut.\GEN_NP[7].u_np.$procmux$674_Y
|
|
New ports: A=3'110, B=18'001010011100101000, Y=$flatten\dut.\GEN_NP[7].u_np.$procmux$674_Y [2:0]
|
|
New connections: $flatten\dut.\GEN_NP[7].u_np.$procmux$674_Y [3] = 1'0
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 8 changes.
|
|
|
|
5.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 991 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~82 debug messages>
|
|
|
|
5.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 991 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1573 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1382 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1916 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1193 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1752 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1025 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$2087 ($sdffe) from module harness_neural_processor_array.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$982 ($sdffe) from module harness_neural_processor_array.
|
|
|
|
5.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~8 debug messages>
|
|
|
|
5.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~82 debug messages>
|
|
|
|
5.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 991 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.32.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$5e21cfa2ff6d644e10a0fc1dcdb22e5eb183bcd3\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
No more expansions possible.
|
|
<suppressed ~4759 debug messages>
|
|
|
|
5.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~2344 debug messages>
|
|
|
|
5.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 12741 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 11501 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 11165 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
<suppressed ~4728 debug messages>
|
|
Removed a total of 1576 cells.
|
|
|
|
5.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 5921 unused cells and 5256 unused wires.
|
|
<suppressed ~5922 debug messages>
|
|
|
|
5.34.5. Finished fast OPT passes.
|
|
|
|
5.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
5.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 5244 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.38.2. Continuing TECHMAP pass.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $paramod$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
|
|
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~3200 debug messages>
|
|
|
|
5.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
5.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in harness_neural_processor_array.
|
|
|
|
5.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
5.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 14761 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_processor_array...
|
|
Found and reported 0 problems.
|
|
|
|
5.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
5.46. Executing ABC9 pass.
|
|
|
|
5.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.3. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module harness_neural_processor_array.
|
|
Found 0 SCCs.
|
|
|
|
5.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.46.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
5.46.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.46.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
5.46.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
5.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
5.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
5.46.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
5.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
5.46.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
5.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.46.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.46.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
5.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
5.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
5.46.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.46.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
5.46.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
5.46.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
<suppressed ~18 debug messages>
|
|
|
|
5.46.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 59 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Computing hashes of 57 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
5.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
5.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.46.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 57 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
5.46.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
5.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_neural_processor_array..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
5.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_neural_processor_array.
|
|
Performed a total of 0 changes.
|
|
|
|
5.46.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_neural_processor_array'.
|
|
Computing hashes of 57 cells of `\harness_neural_processor_array'.
|
|
Finding duplicate cells in `\harness_neural_processor_array'.
|
|
Removed a total of 0 cells.
|
|
|
|
5.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
5.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_neural_processor_array..
|
|
|
|
5.46.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_neural_processor_array.
|
|
|
|
5.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
5.46.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_neural_processor_array: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
5.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_neural_processor_array: replaced 842 cells with 3710 new cells, skipped 4402 cells.
|
|
replaced 3 cell types:
|
|
63 $_MUX_
|
|
728 $_OR_
|
|
51 $_XOR_
|
|
not replaced 6 cell types:
|
|
304 $_AND_
|
|
113 $_NOT_
|
|
9 $scopeinfo
|
|
3096 TRELLIS_FF
|
|
64 MULT18X18D
|
|
816 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
5.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
5.46.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 1374 AND gates and 11735 wires from module `harness_neural_processor_array' to a netlist network with 4130 inputs and 3087 outputs.
|
|
|
|
5.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
5.46.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 4130/ 3087 and = 1310 lev = 19 (0.07) mem = 0.28 MB box = 816 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 4130/ 3087 and = 1567 lev = 8 (0.05) mem = 0.27 MB ch = 188 box = 768 bb = 0
|
|
ABC: cst = 0 cls = 182 lit = 188 unused = 7631 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 1567. Ch = 182. Total mem = 2.95 MB. Peak cut mem = 0.07 MB.
|
|
ABC: P: Del = 2089.00. Ar = 776.0. Edge = 1240. Cut = 15022. T = 0.00 sec
|
|
ABC: P: Del = 2089.00. Ar = 761.0. Edge = 1246. Cut = 14995. T = 0.00 sec
|
|
ABC: P: Del = 2089.00. Ar = 535.0. Edge = 1222. Cut = 21374. T = 0.00 sec
|
|
ABC: F: Del = 2048.00. Ar = 369.0. Edge = 1205. Cut = 18307. T = 0.00 sec
|
|
ABC: A: Del = 2048.00. Ar = 367.0. Edge = 1157. Cut = 16456. T = 0.00 sec
|
|
ABC: A: Del = 2048.00. Ar = 366.0. Edge = 1155. Cut = 16702. T = 0.00 sec
|
|
ABC: Total time = 0.01 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: The network is not changed by "&mfs".
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 4130/ 3087 and = 1033 lev = 8 (0.05) mem = 0.26 MB box = 768 bb = 0
|
|
ABC: Mapping (K=6) : lut = 311 edge = 1155 lev = 4 (0.03) levB = 16 mem = 0.07 MB
|
|
ABC: LUT = 311 : 2=42 13.5 % 3=55 17.7 % 4=169 54.3 % 5=40 12.9 % 6=5 1.6 % Ave = 3.71
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.04 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.14 seconds, total: 0.14 seconds
|
|
|
|
5.46.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 1419 unused cells and 16382 unused wires.
|
|
|
|
5.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 319
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 768
|
|
ABC RESULTS: input signals: 179
|
|
ABC RESULTS: output signals: 473
|
|
<suppressed ~14482 debug messages>
|
|
Removing temp directory.
|
|
|
|
5.46.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.46.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~774 debug messages>
|
|
Removed 100 unused cells and 21351 unused wires.
|
|
|
|
5.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
5.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
5.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
|
|
Using template $paramod$2bf796e0fd6e6f7f76aac424a34e617ed5d61822$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
|
|
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5$lut for cells of type $lut.
|
|
Using template $paramod$d753d16024e02c7baea403774ac6e5fa3c938085$lut for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
|
|
Using template $paramod$e7acaad2d79ca9d6583d9edc46f9553c36f919ec$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110110 for cells of type $lut.
|
|
Using template $paramod$62e915a069c19bae9e977a76393d7673b515df0a$lut for cells of type $lut.
|
|
Using template $paramod$b1675db71461117a4f055bb2700b23d984ad2ee5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
|
|
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut.
|
|
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut.
|
|
Using template $paramod$391a873e8e5cbf5b8eb53e7e280c7b458b9f83e8$lut for cells of type $lut.
|
|
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
|
|
Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut.
|
|
Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
|
|
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut.
|
|
Using template $paramod$00ad7806bfcafde31473cc654753152df84d6423$lut for cells of type $lut.
|
|
Using template $paramod$5025f64545d78aea19c4f26cb3afe3b59658fc6a$lut for cells of type $lut.
|
|
Using template $paramod$6df2bdde0dda2853f5f5b9a550fd1a1d6cc3fb87$lut for cells of type $lut.
|
|
Using template $paramod$0ee76de659bb16de1a03c8c306f484f5819fdcc7$lut for cells of type $lut.
|
|
Using template $paramod$b0928b578fc22552ea42f84c14bfc4a08755e21f$lut for cells of type $lut.
|
|
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c$lut for cells of type $lut.
|
|
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b$lut for cells of type $lut.
|
|
Using template $paramod$c36f326663a38d09ba22f539110c9a7d793c9b2a$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~1054 debug messages>
|
|
|
|
5.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in harness_neural_processor_array.
|
|
Optimizing lut $abc$29320$lut$aiger29319$6453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o6942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o7267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$29320$lut$aiger$o7267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o7058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$29320$lut$aiger$o7051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o6942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$29347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o6942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o6916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$29367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger$o8403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger$o7158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$29320$lut$aiger29319$7023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$29320$lut$aiger29319$6868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Removed 0 unused cells and 758 unused wires.
|
|
|
|
5.49. Executing AUTONAME pass.
|
|
Renamed 5533 objects in module harness_neural_processor_array.
|
|
<suppressed ~5533 debug messages>
|
|
|
|
5.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `harness_neural_processor_array'. Setting top module to harness_neural_processor_array.
|
|
|
|
5.50.1. Analyzing design hierarchy..
|
|
Top module: \harness_neural_processor_array
|
|
|
|
5.50.2. Analyzing design hierarchy..
|
|
Top module: \harness_neural_processor_array
|
|
Removed 0 unused modules.
|
|
|
|
5.51. Printing statistics.
|
|
|
|
=== harness_neural_processor_array ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
2031 wires
|
|
21721 wire bits
|
|
2031 public wires
|
|
21721 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
73 cells
|
|
9 $scopeinfo
|
|
64 MULT18X18D
|
|
4245 submodules
|
|
768 CCU2C
|
|
5 L6MUX21
|
|
374 LUT4
|
|
50 PFUMX
|
|
3048 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
73 harness_neural_processor_array
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
2031 wires
|
|
21721 wire bits
|
|
2031 public wires
|
|
21721 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
73 cells
|
|
9 $scopeinfo
|
|
64 MULT18X18D
|
|
4245 submodules
|
|
768 CCU2C
|
|
5 L6MUX21
|
|
374 LUT4
|
|
50 PFUMX
|
|
3048 TRELLIS_FF
|
|
|
|
5.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_neural_processor_array...
|
|
Found and reported 0 problems.
|
|
|
|
5.53. Executing JSON backend.
|
|
|
|
Warnings: 36 unique messages, 40 total
|
|
End of script. Logfile hash: 89f94b243a, time: 1.30s, user: 1.18s, system: 0.03s, MEM: 127.17 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 15% 24x opt_clean (0 sec), 13% 23x read_verilog (0 sec), ...
|