micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
299 lines
11 KiB
Verilog
299 lines
11 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// GRAPH FORMAT TESTBENCH (Phase G2)
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//
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// Validates the Type #2 (graph) on-disk data format from §4.2/§4.3
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// of the spec, byte-exact, through the REAL memory stack
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// (int8_memory_access + memory_interface + psram_controller +
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// psram_model) -- same harness as sim/int8_psram_integration_tb.v.
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// No new RTL: this phase is about the FORMAT, not new hardware.
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//
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// Graph under test is the worked example from §3:
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// 4 inputs (id 0..3). n4 = f(x0*5 + x1*(-3) + bias=2), relu.
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// n5 = f(act[n4]*2 + x2*7 + bias=0), none. output = n5 (id 5).
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//
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// Graph descriptor table (11 bytes/entry, MSB-first, entries in
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// out_id order) at table_base = 0x000000:
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// entry0 (n4, out_id=4): conn_ptr=0x000100 n_conn=2 out_id=4
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// activation=ACT_RELU(1) bias=2 reserved=0
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// entry1 (n5, out_id=5): conn_ptr=0x000108 n_conn=2 out_id=5
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// activation=ACT_NONE(0) bias=0 reserved=0
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//
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// Edge blocks (4 bytes/edge: src_id uint16 BE, weight int8,
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// reserved=0):
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// n4 @ 0x000100: (src=0,w=5), (src=1,w=-3)
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// n5 @ 0x000108: (src=4,w=2), (src=2,w=7)
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// ================================================================
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 16;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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localparam ACT_NONE = 8'd0;
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localparam ACT_RELU = 8'd1;
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reg clk;
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reg rst;
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reg req;
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reg wr;
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reg [ADDR_WIDTH-1:0] addr;
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reg signed [7:0] wdata;
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wire signed [7:0] rdata;
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wire ready;
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wire mem_req;
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wire mem_wr;
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wire [ADDR_WIDTH-1:0] mem_addr;
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wire [DATA_WIDTH-1:0] mem_wdata;
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wire mem_lb_n;
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wire mem_ub_n;
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wire [DATA_WIDTH-1:0] mem_rdata;
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wire mem_ready;
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wire psram_mem_req;
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wire psram_mem_wr;
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wire [ADDR_WIDTH-1:0] psram_mem_addr;
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wire [DATA_WIDTH-1:0] psram_mem_wdata;
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wire psram_mem_lb_n;
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wire psram_mem_ub_n;
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wire [DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n;
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wire psram_oe_n;
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wire psram_we_n;
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wire psram_lb_n;
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wire psram_ub_n;
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wire psram_zz_n;
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int8_memory_access #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) int8_access (
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.clk(clk), .rst(rst),
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.req(req), .wr(wr), .addr(addr), .wdata(wdata),
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.rdata(rdata), .ready(ready),
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.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
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.mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
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.mem_rdata(mem_rdata), .mem_ready(mem_ready)
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);
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)
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) memory_if (
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.clk(clk), .rst(rst),
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.req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata),
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.lb_n(mem_lb_n), .ub_n(mem_ub_n),
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.rdata(mem_rdata), .ready(mem_ready),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr), .mem_addr(psram_mem_addr),
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.mem_wdata(psram_mem_wdata), .mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready)
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);
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psram_controller #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH), .CLK_FREQ_MHZ(80)
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) psram_ctrl (
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.clk(clk), .rst(rst),
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.mem_req(psram_mem_req), .mem_wr(psram_mem_wr), .mem_addr(psram_mem_addr),
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.mem_wdata(psram_mem_wdata), .mem_lb_n(psram_mem_lb_n), .mem_ub_n(psram_mem_ub_n),
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.mem_rdata(psram_mem_rdata), .mem_ready(psram_mem_ready),
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.psram_a(psram_a), .psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n)
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);
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH), .DEPTH(16384)
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) psram (
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.clk(clk), .a(psram_a), .dq(psram_dq),
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.ce_n(psram_ce_n), .oe_n(psram_oe_n), .we_n(psram_we_n),
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.lb_n(psram_lb_n), .ub_n(psram_ub_n), .zz_n(psram_zz_n)
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);
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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integer errors;
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task write_byte(input [ADDR_WIDTH-1:0] byte_addr, input [7:0] data);
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begin
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@(posedge clk);
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addr <= byte_addr;
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wdata <= $signed(data);
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wr <= 1'b1;
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req <= 1'b1;
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@(posedge clk);
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req <= 1'b0;
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wait (ready);
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@(posedge clk);
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end
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endtask
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task read_byte(input [ADDR_WIDTH-1:0] byte_addr, input [7:0] expected, input [255:0] name);
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begin
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@(posedge clk);
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addr <= byte_addr;
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wr <= 1'b0;
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req <= 1'b1;
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@(posedge clk);
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req <= 1'b0;
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wait (ready);
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if (rdata !== $signed(expected)) begin
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$display("FAIL %0s addr=0x%06x expected=0x%02x got=0x%02x", name, byte_addr, expected, rdata);
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errors = errors + 1;
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end else begin
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$display("PASS %0s addr=0x%06x data=0x%02x", name, byte_addr, rdata);
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end
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@(posedge clk);
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end
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endtask
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// §4.2 graph descriptor entry: 11 bytes, MSB-first.
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task write_graph_desc(
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input [ADDR_WIDTH-1:0] base,
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input [23:0] conn_ptr,
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input [15:0] n_conn,
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input [15:0] out_id,
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input [7:0] activation,
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input [7:0] bias
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);
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begin
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write_byte(base + 0, conn_ptr[23:16]);
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write_byte(base + 1, conn_ptr[15:8]);
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write_byte(base + 2, conn_ptr[7:0]);
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write_byte(base + 3, n_conn[15:8]);
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write_byte(base + 4, n_conn[7:0]);
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write_byte(base + 5, out_id[15:8]);
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write_byte(base + 6, out_id[7:0]);
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write_byte(base + 7, activation);
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write_byte(base + 8, bias);
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write_byte(base + 9, 8'h00); // reserved
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write_byte(base + 10, 8'h00); // reserved
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end
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endtask
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// §4.3 edge: 4 bytes, src_id uint16 BE, weight int8, reserved.
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task write_edge(
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input [ADDR_WIDTH-1:0] base,
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input [15:0] src_id,
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input [7:0] weight
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);
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begin
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write_byte(base + 0, src_id[15:8]);
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write_byte(base + 1, src_id[7:0]);
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write_byte(base + 2, weight);
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write_byte(base + 3, 8'h00); // reserved
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end
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endtask
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localparam TABLE_BASE = 23'h000000;
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localparam N4_EDGES = 23'h000100;
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localparam N5_EDGES = 23'h000108;
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initial begin
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errors = 0;
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req = 1'b0; wr = 1'b0; addr = 0; wdata = 0;
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rst = 1'b1;
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repeat (5) @(posedge clk);
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rst = 1'b0;
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wait (psram_ctrl.state == psram_ctrl.STATE_IDLE);
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$display("");
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$display("========================================");
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$display("GRAPH FORMAT (Type #2) BYTE-EXACT TEST");
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$display("========================================");
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$display("");
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// ---- write the descriptor table (2 entries) ----
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write_graph_desc(TABLE_BASE + 0*11, N4_EDGES, 16'd2, 16'd4, ACT_RELU, 8'sd2);
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write_graph_desc(TABLE_BASE + 1*11, N5_EDGES, 16'd2, 16'd5, ACT_NONE, 8'sd0);
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// ---- write the edge blocks ----
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write_edge(N4_EDGES + 0*4, 16'd0, 8'sd5);
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write_edge(N4_EDGES + 1*4, 16'd1, -8'sd3);
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write_edge(N5_EDGES + 0*4, 16'd4, 8'sd2);
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write_edge(N5_EDGES + 1*4, 16'd2, 8'sd7);
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$display("-- write phase done, reading back byte-exact --");
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$display("");
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// ---- read back entry 0 (n4) byte-exact ----
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read_byte(TABLE_BASE+0, 8'h00, "n4.conn_ptr[23:16]");
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read_byte(TABLE_BASE+1, 8'h01, "n4.conn_ptr[15:8]");
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read_byte(TABLE_BASE+2, 8'h00, "n4.conn_ptr[7:0]");
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read_byte(TABLE_BASE+3, 8'h00, "n4.n_conn[15:8]");
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read_byte(TABLE_BASE+4, 8'h02, "n4.n_conn[7:0]");
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read_byte(TABLE_BASE+5, 8'h00, "n4.out_id[15:8]");
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read_byte(TABLE_BASE+6, 8'h04, "n4.out_id[7:0]");
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read_byte(TABLE_BASE+7, ACT_RELU, "n4.activation");
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read_byte(TABLE_BASE+8, 8'h02, "n4.bias");
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read_byte(TABLE_BASE+9, 8'h00, "n4.reserved0");
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read_byte(TABLE_BASE+10, 8'h00, "n4.reserved1");
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// ---- read back entry 1 (n5) byte-exact ----
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read_byte(TABLE_BASE+11, 8'h00, "n5.conn_ptr[23:16]");
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read_byte(TABLE_BASE+12, 8'h01, "n5.conn_ptr[15:8]");
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read_byte(TABLE_BASE+13, 8'h08, "n5.conn_ptr[7:0]");
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read_byte(TABLE_BASE+14, 8'h00, "n5.n_conn[15:8]");
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read_byte(TABLE_BASE+15, 8'h02, "n5.n_conn[7:0]");
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read_byte(TABLE_BASE+16, 8'h00, "n5.out_id[15:8]");
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read_byte(TABLE_BASE+17, 8'h05, "n5.out_id[7:0]");
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read_byte(TABLE_BASE+18, ACT_NONE, "n5.activation");
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read_byte(TABLE_BASE+19, 8'h00, "n5.bias");
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read_byte(TABLE_BASE+20, 8'h00, "n5.reserved0");
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read_byte(TABLE_BASE+21, 8'h00, "n5.reserved1");
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// ---- read back n4's edges byte-exact ----
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read_byte(N4_EDGES+0, 8'h00, "n4.e0.src_id[15:8]");
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read_byte(N4_EDGES+1, 8'h00, "n4.e0.src_id[7:0]");
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read_byte(N4_EDGES+2, 8'h05, "n4.e0.weight");
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read_byte(N4_EDGES+3, 8'h00, "n4.e0.reserved");
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read_byte(N4_EDGES+4, 8'h00, "n4.e1.src_id[15:8]");
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read_byte(N4_EDGES+5, 8'h01, "n4.e1.src_id[7:0]");
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read_byte(N4_EDGES+6, 8'hFD, "n4.e1.weight(-3)");
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read_byte(N4_EDGES+7, 8'h00, "n4.e1.reserved");
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// ---- read back n5's edges byte-exact ----
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read_byte(N5_EDGES+0, 8'h00, "n5.e0.src_id[15:8]");
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read_byte(N5_EDGES+1, 8'h04, "n5.e0.src_id[7:0]");
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read_byte(N5_EDGES+2, 8'h02, "n5.e0.weight");
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read_byte(N5_EDGES+3, 8'h00, "n5.e0.reserved");
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read_byte(N5_EDGES+4, 8'h00, "n5.e1.src_id[15:8]");
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read_byte(N5_EDGES+5, 8'h02, "n5.e1.src_id[7:0]");
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read_byte(N5_EDGES+6, 8'h07, "n5.e1.weight");
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read_byte(N5_EDGES+7, 8'h00, "n5.e1.reserved");
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// ---- overlap/independence sanity check: rewriting n4's
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// bias must not disturb n5's descriptor or any edge byte ----
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write_byte(TABLE_BASE+8, 8'sd9);
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read_byte(TABLE_BASE+8, 8'h09, "n4.bias overwritten");
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read_byte(TABLE_BASE+19, 8'h00, "n5.bias unaffected by n4 rewrite");
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read_byte(N4_EDGES+2, 8'h05, "n4.e0.weight unaffected by n4 desc rewrite");
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$display("");
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if (errors == 0) begin
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$display("========================================");
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$display("GRAPH FORMAT TEST PASSED (0 errors)");
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$display("========================================");
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end else begin
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$display("========================================");
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$display("GRAPH FORMAT TEST FAILED (%0d errors)", errors);
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$display("========================================");
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$fatal;
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end
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$finish;
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end
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endmodule
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