micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
455 lines
12 KiB
Verilog
455 lines
12 KiB
Verilog
`timescale 1ns/1ps
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 16;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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// ============================================================
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// Clock / Reset
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// ============================================================
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reg clk;
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reg rst;
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// ============================================================
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// INT8 interface
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// ============================================================
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reg req;
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reg wr;
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reg [ADDR_WIDTH-1:0] addr;
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reg signed [7:0] wdata;
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wire signed [7:0] rdata;
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wire ready;
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// ============================================================
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// memory_interface
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// ============================================================
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wire mem_req;
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wire mem_wr;
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wire [ADDR_WIDTH-1:0] mem_addr;
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wire [DATA_WIDTH-1:0] mem_wdata;
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wire mem_lb_n;
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wire mem_ub_n;
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wire [DATA_WIDTH-1:0] mem_rdata;
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wire mem_ready;
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// ============================================================
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// Memory interface -> PSRAM controller
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// ============================================================
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wire psram_mem_req;
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wire psram_mem_wr;
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wire [ADDR_WIDTH-1:0] psram_mem_addr;
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wire [DATA_WIDTH-1:0] psram_mem_wdata;
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wire psram_mem_lb_n;
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wire psram_mem_ub_n;
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wire [DATA_WIDTH-1:0] psram_mem_rdata;
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wire psram_mem_ready;
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// ============================================================
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// PSRAM physical interface
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// ============================================================
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n;
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wire psram_oe_n;
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wire psram_we_n;
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wire psram_lb_n;
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wire psram_ub_n;
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wire psram_zz_n;
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// ============================================================
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// INT8 MEMORY ACCESS
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// ============================================================
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int8_memory_access #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) int8_access (
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.clk (clk),
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.rst (rst),
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.req (req),
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.wr (wr),
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.addr (addr),
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.wdata (wdata),
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.rdata (rdata),
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.ready (ready),
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.mem_req (mem_req),
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.mem_wr (mem_wr),
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.mem_addr (mem_addr),
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.mem_wdata (mem_wdata),
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.mem_lb_n (mem_lb_n),
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.mem_ub_n (mem_ub_n),
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.mem_rdata (mem_rdata),
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.mem_ready (mem_ready)
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);
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// ============================================================
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// MEMORY INTERFACE
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// ============================================================
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memory_interface #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) memory_if (
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.clk (clk),
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.rst (rst),
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.req (mem_req),
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.wr (mem_wr),
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.addr (mem_addr),
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.wdata (mem_wdata),
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.lb_n (mem_lb_n),
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.ub_n (mem_ub_n),
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.rdata (mem_rdata),
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.ready (mem_ready),
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.mem_req (psram_mem_req),
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.mem_wr (psram_mem_wr),
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.mem_addr (psram_mem_addr),
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.mem_wdata (psram_mem_wdata),
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.mem_lb_n (psram_mem_lb_n),
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.mem_ub_n (psram_mem_ub_n),
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.mem_rdata (psram_mem_rdata),
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.mem_ready (psram_mem_ready)
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);
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// ============================================================
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// PSRAM CONTROLLER
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// ============================================================
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psram_controller #(
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.ADDR_WIDTH (ADDR_WIDTH),
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.DATA_WIDTH (DATA_WIDTH),
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.CLK_FREQ_MHZ (80)
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) psram_ctrl (
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.clk (clk),
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.rst (rst),
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.mem_req (psram_mem_req),
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.mem_wr (psram_mem_wr),
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.mem_addr (psram_mem_addr),
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.mem_wdata (psram_mem_wdata),
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.mem_lb_n (psram_mem_lb_n),
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.mem_ub_n (psram_mem_ub_n),
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.mem_rdata (psram_mem_rdata),
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.mem_ready (psram_mem_ready),
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.psram_a (psram_a),
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.psram_dq (psram_dq),
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.psram_ce_n(psram_ce_n),
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.psram_oe_n(psram_oe_n),
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.psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n),
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.psram_ub_n(psram_ub_n),
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.psram_zz_n(psram_zz_n)
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);
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// ============================================================
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// PSRAM MODEL
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// ============================================================
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(16384)
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) psram (
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.clk (clk),
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.a (psram_a),
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.dq (psram_dq),
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.ce_n (psram_ce_n),
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.oe_n (psram_oe_n),
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.we_n (psram_we_n),
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.lb_n (psram_lb_n),
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.ub_n (psram_ub_n),
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.zz_n (psram_zz_n)
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);
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// ============================================================
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// Clock
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// ============================================================
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0)
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clk = ~clk;
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end
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// ============================================================
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// VCD
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// ============================================================
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initial begin
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$dumpfile("sim/int8_psram_integration.vcd");
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$dumpvars(0, tb);
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end
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// ============================================================
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// Write INT8
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// ============================================================
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task write_byte;
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input [ADDR_WIDTH-1:0] byte_addr;
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input signed [7:0] data;
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begin
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@(posedge clk);
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addr <= byte_addr;
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wdata <= data;
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wr <= 1'b1;
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req <= 1'b1;
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@(posedge clk);
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req <= 1'b0;
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wait (ready);
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$display(
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"WRITE BYTE addr=0x%08x data=0x%02x PASS",
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byte_addr,
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data
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);
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@(posedge clk);
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end
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endtask
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// ============================================================
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// Read INT8
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// ============================================================
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task read_byte;
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input [ADDR_WIDTH-1:0] byte_addr;
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input signed [7:0] expected;
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begin
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@(posedge clk);
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addr <= byte_addr;
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wr <= 1'b0;
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req <= 1'b1;
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@(posedge clk);
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req <= 1'b0;
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wait (ready);
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if (rdata !== expected) begin
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$display(
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"READ BYTE addr=0x%08x FAIL got=0x%02x expected=0x%02x",
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byte_addr,
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rdata,
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expected
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);
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$fatal;
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end else begin
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$display(
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"READ BYTE addr=0x%08x data=0x%02x PASS",
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byte_addr,
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rdata
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);
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end
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@(posedge clk);
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end
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endtask
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// ============================================================
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// Test
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// ============================================================
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integer i;
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integer test_addr;
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reg signed [7:0] test_data;
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initial begin
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req = 1'b0;
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wr = 1'b0;
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addr = 0;
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wdata = 0;
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rst = 1'b1;
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repeat (5)
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@(posedge clk);
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rst = 1'b0;
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$display("");
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$display("========================================");
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$display("INT8 + PSRAM FULL INTEGRATION TEST");
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$display("========================================");
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$display("");
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// --------------------------------------------------------
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// Wait for PSRAM initialization
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// --------------------------------------------------------
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wait (psram_ctrl.state == psram_ctrl.STATE_IDLE);
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$display("PSRAM initialization complete");
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$display("");
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// ========================================================
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// BASIC INT8 PACKING
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// ========================================================
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write_byte(22'h000000, 8'h12);
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write_byte(22'h000001, 8'h34);
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write_byte(22'h000002, 8'h56);
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write_byte(22'h000003, 8'h78);
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read_byte(22'h000000, 8'h12);
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read_byte(22'h000001, 8'h34);
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read_byte(22'h000002, 8'h56);
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read_byte(22'h000003, 8'h78);
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// ========================================================
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// BYTE PRESERVATION
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// ========================================================
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write_byte(22'h000010, 8'h34);
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write_byte(22'h000011, 8'h12);
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write_byte(22'h000010, 8'hAA);
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read_byte(22'h000010, 8'hAA);
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read_byte(22'h000011, 8'h12);
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write_byte(22'h000011, 8'hBB);
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read_byte(22'h000010, 8'hAA);
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read_byte(22'h000011, 8'hBB);
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// ========================================================
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// SIGNED INT8
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// ========================================================
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write_byte(22'h000020, -8'sd1);
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write_byte(22'h000021, -8'sd128);
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write_byte(22'h000022, 8'sd127);
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read_byte(22'h000020, -8'sd1);
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read_byte(22'h000021, -8'sd128);
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read_byte(22'h000022, 8'sd127);
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// ========================================================
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// SPARSE ADDRESSES
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// ========================================================
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write_byte(22'h000100, 8'h11);
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write_byte(22'h000101, 8'h22);
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write_byte(22'h001000, 8'h33);
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write_byte(22'h001001, 8'h44);
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write_byte(22'h003FFE, 8'h55);
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write_byte(22'h003FFF, 8'h66);
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read_byte(22'h000100, 8'h11);
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read_byte(22'h000101, 8'h22);
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read_byte(22'h001000, 8'h33);
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read_byte(22'h001001, 8'h44);
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read_byte(22'h003FFE, 8'h55);
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read_byte(22'h003FFF, 8'h66);
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// ========================================================
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// STRESS TEST
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// ========================================================
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$display("");
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$display("========================================");
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$display("INT8 PSRAM STRESS TEST");
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$display("2048 WRITE + READ BYTE TRANSACTIONS");
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$display("========================================");
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$display("");
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for (i = 0; i < 2048; i = i + 1) begin
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test_addr =
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((i * 7919) ^ (i << 5)) & 16'h7FFF;
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test_data =
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((i * 1237) ^ 8'hA5);
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write_byte(
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test_addr,
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test_data
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);
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read_byte(
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test_addr,
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test_data
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);
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if ((i % 128) == 0)
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$display(
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"STRESS %0d / 2048 PASS",
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i
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);
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end
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// ========================================================
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// Final result
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// ========================================================
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$display("");
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$display("========================================");
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$display("INT8 + PSRAM INTEGRATION TEST PASSED");
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$display("BYTE ADDRESSING : PASS");
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$display("LB# / UB# : PASS");
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$display("INT8 PACKING : PASS");
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$display("BYTE PRESERVATION : PASS");
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$display("SIGNED INT8 : PASS");
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$display("SPARSE ADDRESSES : PASS");
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$display("2048 STRESS : PASS");
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$display("========================================");
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$display("");
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$finish;
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end
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endmodule |