micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
51 lines
1.8 KiB
Verilog
51 lines
1.8 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// CRC32_BYTE - combinational one-byte CRC32 update (IEEE 802.3 /
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// zlib.crc32 algorithm: reflected polynomial 0xEDB88320, MSB-first
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// byte order, init 0xFFFFFFFF, final XOR 0xFFFFFFFF applied by the
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// CALLER when reading out the finished CRC, not baked in here so
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// this block is a pure, reusable byte-update step).
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//
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// This exact reflected-polynomial bit-serial-per-byte construction
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// is the standard, widely-documented way to compute the same CRC32
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// zlib/PNG/Ethernet use; it is NOT re-derived from the flash
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// subsystem's own design -- the independent oracle for this
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// project is tools/flash_catalog/oracle.py's `crc32()`, which calls
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// Python's stdlib `zlib.crc32` (a completely separate implementation
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// in a different language). The two are cross-checked bit-for-bit
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// by sim/crc32_tb.v -- see WORKLOG.md's F4 entry for the numbers.
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//
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// Usage: register `crc_out` into your own accumulator on the cycle
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// a new byte is valid, seeded at 32'hFFFFFFFF before the first byte
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// of a message; XOR the final accumulated value with 32'hFFFFFFFF
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// to get the conventional CRC32 result.
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// ================================================================
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module crc32_byte (
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input wire [31:0] crc_in,
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input wire [7:0] data,
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output wire [31:0] crc_out
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);
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function [31:0] next_crc;
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input [31:0] c_in;
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input [7:0] d;
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reg [31:0] c;
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integer k;
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begin
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c = c_in ^ {24'h0, d};
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for (k = 0; k < 8; k = k + 1) begin
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if (c[0])
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c = (c >> 1) ^ 32'hEDB88320;
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else
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c = c >> 1;
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end
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next_crc = c;
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end
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endfunction
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assign crc_out = next_crc(crc_in, data);
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endmodule
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