micheleandClaude Sonnet 5
8ad04987de
Implements the highest-leverage fix from EXP-0080's bottleneck analysis: act_tile_fetch.v now packs 2 consecutive tiles per DDR3 burst (even tile low 64 bits, odd tile high 64 bits) instead of 1 tile per burst, halving real DDR3 bytes-per-useful-byte. Timing-safe by construction: the tile-index select bit is registered at request time, long before the real DDR3 round-trip completes, never racing the arriving read data (unlike the runtime part-select pattern EXP-0079 deliberately avoided). Re-verified at all 3 levels (isolated engine 8/8, packed_slot.v 9/9 with bit-identical results to EXP-0079, full N=2 system on real DDR3 8/8) -- the real JEDEC trace now shows no half-burst padding, direct confirmation the fix works in practice, not just in theory. Also: real device data gathered on this package's I/O bank layout (only 5 banks total, 14/15/16/34/35) informing the next bandwidth step (32-bit-wide single controller recommended over a second independent channel, given the pin/logic cost comparison). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC