502 lines
14 KiB
Verilog
502 lines
14 KiB
Verilog
`timescale 1ns/1ps
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module psram_model #(
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parameter ADDR_WIDTH = 22,
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parameter DATA_WIDTH = 16,
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parameter DEPTH = 16384
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)(
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input wire clk,
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input wire [ADDR_WIDTH-1:0] a,
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inout wire [DATA_WIDTH-1:0] dq,
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input wire ce_n,
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input wire oe_n,
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input wire we_n,
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input wire lb_n,
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input wire ub_n,
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input wire zz_n
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);
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// ============================================================
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// IS66WVE4M16EBLL-70BLI - Rev. D3
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// ============================================================
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localparam realtime TAA_NS = 70.0;
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localparam realtime TRC_NS = 70.0;
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localparam realtime TOE_NS = 20.0;
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localparam realtime TOH_NS = 5.0;
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localparam realtime TLZ_NS = 10.0;
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localparam realtime THZ_NS = 8.0;
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localparam realtime TWC_NS = 70.0;
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localparam realtime TAW_NS = 70.0;
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localparam realtime TCW_NS = 70.0;
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localparam realtime TWP_NS = 46.0;
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localparam realtime TDW_NS = 23.0;
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localparam realtime TDH_NS = 0.0;
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localparam realtime TWR_NS = 0.0;
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localparam realtime TWPH_NS = 10.0;
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localparam realtime TPU_NS = 150000.0;
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// ============================================================
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// Memory
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// ============================================================
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reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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reg [DATA_WIDTH-1:0] dq_out;
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reg dq_oe;
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integer i;
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assign dq = dq_oe ? dq_out : {DATA_WIDTH{1'bz}};
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// ============================================================
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// Timing state
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// ============================================================
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realtime powerup_time;
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realtime ce_low_time;
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realtime ce_high_time;
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realtime oe_low_time;
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realtime oe_high_time;
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realtime we_low_time;
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realtime we_high_time;
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realtime last_read_start;
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realtime last_write_start;
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realtime addr_valid_time;
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realtime data_valid_time;
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reg read_active;
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reg write_active;
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reg [ADDR_WIDTH-1:0] active_addr;
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reg [DATA_WIDTH-1:0] active_wdata;
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// ============================================================
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// Initialization
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// ============================================================
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initial begin
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for (i = 0; i < DEPTH; i = i + 1)
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mem[i] = 16'h0000;
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dq_out = 16'h0000;
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dq_oe = 1'b0;
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powerup_time = $realtime;
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ce_low_time = 0.0;
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ce_high_time = 0.0;
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oe_low_time = 0.0;
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oe_high_time = 0.0;
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we_low_time = 0.0;
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we_high_time = 0.0;
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last_read_start = -1.0;
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last_write_start = -1.0;
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addr_valid_time = 0.0;
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data_valid_time = 0.0;
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read_active = 1'b0;
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write_active = 1'b0;
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active_addr = 0;
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active_wdata = 0;
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end
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// ============================================================
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// FUNCTIONAL READ MODEL
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// ============================================================
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always @(*) begin
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dq_oe = 1'b0;
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dq_out = 16'h0000;
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if (zz_n &&
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!ce_n &&
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!oe_n &&
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we_n) begin
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if (a < DEPTH) begin
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dq_oe = 1'b1;
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if (!lb_n && !ub_n)
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dq_out = mem[a];
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else if (!lb_n)
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dq_out = {
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8'h00,
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mem[a][7:0]
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};
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else if (!ub_n)
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dq_out = {
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mem[a][15:8],
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8'h00
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};
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end
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end
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end
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// ============================================================
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// CE# FALLING
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// ============================================================
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always @(negedge ce_n) begin
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if (!zz_n) begin
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$display("ERROR: CE# LOW while ZZ# LOW");
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$fatal;
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end
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ce_low_time = $realtime;
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addr_valid_time = $realtime;
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active_addr = a;
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// --------------------------------------------------------
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// READ START
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// --------------------------------------------------------
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if (!oe_n && we_n) begin
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if (($realtime - powerup_time) < TPU_NS) begin
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$display("ERROR: READ before tPU");
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$fatal;
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end
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if (last_read_start >= 0.0) begin
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if (($realtime - last_read_start) < TRC_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tRC violation");
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$display("required = %0.2f ns", TRC_NS);
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$display("actual = %0.2f ns",
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$realtime - last_read_start);
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$display("========================================");
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$fatal;
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end
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end
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last_read_start = $realtime;
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read_active = 1'b1;
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end
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// --------------------------------------------------------
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// WRITE START
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// --------------------------------------------------------
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if (oe_n && !we_n) begin
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if (($realtime - powerup_time) < TPU_NS) begin
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$display("ERROR: WRITE before tPU");
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$fatal;
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end
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if (last_write_start >= 0.0) begin
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if (($realtime - last_write_start) < TWC_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tWC violation");
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$display("required = %0.2f ns", TWC_NS);
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$display("actual = %0.2f ns",
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$realtime - last_write_start);
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$display("========================================");
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$fatal;
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end
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end
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last_write_start = $realtime;
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write_active = 1'b1;
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end
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end
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// ============================================================
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// CE# RISING
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// ============================================================
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always @(posedge ce_n) begin
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realtime access_time;
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ce_high_time = $realtime;
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access_time = $realtime - ce_low_time;
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// --------------------------------------------------------
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// READ END
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// --------------------------------------------------------
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if (read_active) begin
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// tAA
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if (access_time < TAA_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tAA violation");
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$display("required = %0.2f ns", TAA_NS);
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$display("actual = %0.2f ns", access_time);
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$display("========================================");
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$fatal;
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end
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// tOE
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if (($realtime - oe_low_time) < TOE_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tOE violation");
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$display("required = %0.2f ns", TOE_NS);
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$display("actual = %0.2f ns",
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$realtime - oe_low_time);
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$display("========================================");
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$fatal;
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end
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read_active = 1'b0;
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end
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end
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// ============================================================
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// OE# FALLING
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// ============================================================
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always @(negedge oe_n) begin
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if (!zz_n) begin
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$display("ERROR: OE# LOW while ZZ# LOW");
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$fatal;
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end
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if (!ce_n && we_n)
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oe_low_time = $realtime;
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// Illegal combination
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if (!ce_n && !we_n) begin
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$display("");
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$display("========================================");
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$display("PSRAM PROTOCOL ERROR");
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$display("OE# and WE# LOW simultaneously");
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$display("========================================");
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$fatal;
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end
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end
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// ============================================================
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// OE# RISING
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// ============================================================
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always @(posedge oe_n) begin
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oe_high_time = $realtime;
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// Output must remain valid long enough for tOH
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// after address changes. This is checked by the
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// controller access window rather than by forcing
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// an artificial delay into the functional model.
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end
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// ============================================================
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// WE# FALLING
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// ============================================================
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always @(negedge we_n) begin
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if (!zz_n) begin
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$display("ERROR: WE# LOW while ZZ# LOW");
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$fatal;
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end
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if (!ce_n && oe_n) begin
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we_low_time = $realtime;
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active_addr = a;
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active_wdata = dq;
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write_active = 1'b1;
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end
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// Illegal combination
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if (!ce_n && !oe_n) begin
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$display("");
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$display("========================================");
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$display("PSRAM PROTOCOL ERROR");
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$display("OE# and WE# LOW simultaneously");
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$display("========================================");
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$fatal;
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end
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end
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// ============================================================
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// WE# RISING
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// ============================================================
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always @(posedge we_n) begin
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realtime write_width;
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realtime data_setup;
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we_high_time = $realtime;
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if (write_active) begin
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write_width = $realtime - we_low_time;
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// ----------------------------------------------------
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// tWP
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// ----------------------------------------------------
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if (write_width < TWP_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tWP violation");
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$display("required = %0.2f ns", TWP_NS);
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$display("actual = %0.2f ns", write_width);
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$display("========================================");
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$fatal;
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end
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// ----------------------------------------------------
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// tAW
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// ----------------------------------------------------
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if (($realtime - addr_valid_time) < TAW_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tAW violation");
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$display("required = %0.2f ns", TAW_NS);
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$display("actual = %0.2f ns",
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$realtime - addr_valid_time);
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$display("========================================");
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$fatal;
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end
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// ----------------------------------------------------
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// tCW
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// ----------------------------------------------------
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if (($realtime - ce_low_time) < TCW_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tCW violation");
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$display("required = %0.2f ns", TCW_NS);
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$display("actual = %0.2f ns",
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$realtime - ce_low_time);
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$display("========================================");
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$fatal;
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end
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// ----------------------------------------------------
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// tDW
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//
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// Data must be valid before WE# rises.
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// Our controller drives DQ from WE# falling,
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// therefore setup is much larger than 23 ns.
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// ----------------------------------------------------
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data_setup = $realtime - we_low_time;
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if (data_setup < TDW_NS) begin
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$display("");
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$display("========================================");
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$display("PSRAM TIMING ERROR");
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$display("tDW violation");
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$display("required = %0.2f ns", TDW_NS);
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$display("actual = %0.2f ns", data_setup);
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$display("========================================");
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$fatal;
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end
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// ----------------------------------------------------
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// tDH = 0 ns
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// ----------------------------------------------------
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// No additional hold time is required.
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// ----------------------------------------------------
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// Store data
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// ----------------------------------------------------
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if (a !== active_addr) begin
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$display("");
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$display("========================================");
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$display("PSRAM PROTOCOL ERROR");
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$display("ADDRESS CHANGED DURING WRITE");
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$display("========================================");
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$fatal;
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end
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if (a < DEPTH) begin
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if (!lb_n)
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mem[a][7:0] <= dq[7:0];
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if (!ub_n)
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mem[a][15:8] <= dq[15:8];
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end
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write_active = 1'b0;
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end
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end
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// ============================================================
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// ZZ#
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// ============================================================
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always @(negedge zz_n) begin
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if (!ce_n) begin
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$display("");
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$display("========================================");
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$display("PSRAM PROTOCOL ERROR");
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$display("ZZ# LOW while CE# LOW");
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$display("========================================");
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$fatal;
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end
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end
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endmodule |