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FPGA-Neural/hardware/v2/synthesis/harness_n1/nextpnr.log
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micheleandClaude Sonnet 5 3026dcd997 feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep 
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).

Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).

Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.

Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:15:11 +02:00

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Info: Logic utilisation before packing:
Info: Total LUT4s: 251/43848 0%
Info: logic LUTs: 59/43848 0%
Info: carry LUTs: 192/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 409/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 196 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x181a2c1f
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 8/ 72 11%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 409/ 43848 0%
Info: TRELLIS_COMB: 289/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 279 cells, random placement wirelen = 31995.
Info: at initial placer iter 0, wirelen = 1151
Info: at initial placer iter 1, wirelen = 1128
Info: at initial placer iter 2, wirelen = 989
Info: at initial placer iter 3, wirelen = 975
Info: Running main analytical placer, max placement attempts per cell = 65703.
Info: at iteration #1, type ALL: wirelen solved = 965, spread = 6362, legal = 6299; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1001, spread = 6347, legal = 6570; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 1047, spread = 6112, legal = 6089; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 1111, spread = 6479, legal = 6502; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1125, spread = 6467, legal = 6611; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 1231, spread = 6741, legal = 6845; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 1289, spread = 6529, legal = 6566; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 1241, spread = 6711, legal = 6886; time = 0.00s
Info: HeAP Placer Time: 0.06s
Info: of which solving equations: 0.03s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 322, wirelen = 6089
Info: at iteration #5: temp = 0.000000, timing cost = 122, wirelen = 4437
Info: at iteration #10: temp = 0.000000, timing cost = 143, wirelen = 3970
Info: at iteration #15: temp = 0.000000, timing cost = 136, wirelen = 3894
Info: at iteration #16: temp = 0.000000, timing cost = 120, wirelen = 3909
Info: SA placement time 0.09s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 141.70 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.80 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 1.39 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 5443, 5758) |*************************+
Info: [ 5758, 6073) |*****************************************+
Info: [ 6073, 6388) |*****************+
Info: [ 6388, 6703) |****************+
Info: [ 6703, 7018) |*+
Info: [ 7018, 7333) |**+
Info: [ 7333, 7648) |*+
Info: [ 7648, 7963) |******+
Info: [ 7963, 8278) |*******+
Info: [ 8278, 8593) |
Info: [ 8593, 8908) |**************+
Info: [ 8908, 9223) |********+
Info: [ 9223, 9538) |***************
Info: [ 9538, 9853) |**********************************+
Info: [ 9853, 10168) |************************************************************
Info: [ 10168, 10483) |*****************************************+
Info: [ 10483, 10798) |********************************************+
Info: [ 10798, 11113) |*********************+
Info: [ 11113, 11428) |**************+
Info: [ 11428, 11743) |******************************
Info: Checksum: 0x82e6001e
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1745 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 166 833 | 166 833 | 919| 0.30 0.30|
Info: 1953 | 200 1630 | 34 797 | 0| 0.11 0.41|
Info: Routing complete.
Info: Router1 time 0.41s
Info: Checksum: 0xd0a27c89
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.GEN_NP[0].u_np.x0[1]_TRELLIS_FF_Q.Q
Info: routing 1.92 2.32 Net dut.GEN_NP[0].u_np.x0[0][7] (74,43) -> (65,22)
Info: Sink dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.A0
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:99.44-99.46
Info: logic 3.07 5.38 Source dut.GEN_NP[0].u_np.product_comb[7]_MULT18X18D_P9.P1
Info: routing 0.90 6.28 Net dut.GEN_NP[0].u_np.product_comb[7][1] (65,22) -> (65,23)
Info: Sink dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_1.M
Info: Defined in:
Info: hardware/v2/rtl/neural_processor.v:135.34-135.46
Info: setup 0.00 6.28 Source dut.GEN_NP[0].u_np.prod1[7]_TRELLIS_FF_Q_1.M
Info: 3.46 ns logic, 2.82 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 2.56 2.56 Net rst$TRELLIS_IO_IN (67,0) -> (74,32)
Info: Sink dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.C
Info: Defined in:
Info: hardware/v2/synthesis/harness_neural_processor_array.v:30.12-30.15
Info: logic 0.18 2.74 Source dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D.F
Info: routing 0.83 3.57 Net dut.GEN_NP[0].u_np.valid0_TRELLIS_FF_Q_DI_LUT4_D_Z (74,32) -> (83,33)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.75 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.22 3.98 Net dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q_LSR (83,33) -> (83,33)
Info: Sink dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: setup 0.29 4.26 Source dut.GEN_NP[0].u_np.last0_TRELLIS_FF_Q.LSR
Info: 0.65 ns logic, 3.62 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q.Q
Info: routing 1.00 1.39 Net checksum[0]$TRELLIS_IO_OUT (86,33) -> (90,32)
Info: Sink checksum[0]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 1.00 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 159.11 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.26 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 1.39 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6215, 6495) |*********************************************************+
Info: [ 6495, 6775) |*******************************************+
Info: [ 6775, 7055) |***********+
Info: [ 7055, 7335) |+
Info: [ 7335, 7615) |
Info: [ 7615, 7895) |
Info: [ 7895, 8175) |+
Info: [ 8175, 8455) |****+
Info: [ 8455, 8735) |************+
Info: [ 8735, 9015) |**************+
Info: [ 9015, 9295) |***********+
Info: [ 9295, 9575) |****************************+
Info: [ 9575, 9855) |*****************************************************+
Info: [ 9855, 10135) |************************************************************
Info: [ 10135, 10415) |************************************+
Info: [ 10415, 10695) |***************+
Info: [ 10695, 10975) |******************************
Info: [ 10975, 11255) |*********************+
Info: [ 11255, 11535) |**********************+
Info: [ 11535, 11815) |****************************+
Info: Program finished normally.
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