33 lines
555 B
Verilog
33 lines
555 B
Verilog
module top;
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reg clk;
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reg rst;
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reg start;
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reg signed [1023:0] x_bus;
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reg signed [1023:0] w_bus;
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reg signed [15:0] bias;
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wire signed [15:0] y;
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wire busy;
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wire done;
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neuron_parallel #(
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.DATA_WIDTH(16),
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.FRAC_BITS(8),
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.N_INPUTS(64),
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.PARALLEL(8),
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.ACC_WIDTH(40)
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) dut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.w_bus(w_bus),
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.bias(bias),
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.y(y),
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.busy(busy),
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.done(done)
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);
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endmodule |