michele
cfd5e98a0e
tools/fpga_benchmark.py: parametric Yosys + nextpnr-ecp5 benchmark harness for the LFE5U-45F-8BG381 (speed grade -8, 80 MHz target), sweeping PARALLEL over the neuron layer and parsing Fmax/LUT4/DFF/DSP utilization out of the nextpnr report into JSON/CSV. synth/ecp5/p2, p4, p8: real synthesis+PnR results backing the same-price-tier FPGA comparison (P2: 87.88 MHz PASS, P4: 75.01 MHz FAIL, P8: 147.62 MHz PASS -- non-monotonic, dominated by placement noise since the whole design uses <2% of the device's LUT4 fabric at every setting, and P8 notably maps to 0 DSP blocks vs 8/16 for P2/P4). synth/ecp5/top.v: benchmark harness top-level, reworked to generate deterministic non-constant X/weights/bias via `keep`-attributed generate blocks so Yosys can't constant-fold the datapath away. Also adds .gitignore for Python's __pycache__/*.pyc.
120 lines
2.5 KiB
Verilog
120 lines
2.5 KiB
Verilog
module top #(
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parameter DATA_WIDTH = 8,
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parameter N_INPUTS = 256,
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parameter N_NEURONS = 4,
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parameter PARALLEL = 8,
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parameter ACC_WIDTH = 32
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)(
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input wire clk,
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input wire rst,
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input wire start,
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output wire signed [DATA_WIDTH*N_NEURONS-1:0] y_bus,
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output wire busy,
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output wire done
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);
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localparam X_BITS = DATA_WIDTH * N_INPUTS;
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localparam W_BITS = DATA_WIDTH * N_INPUTS * N_NEURONS;
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localparam B_BITS = DATA_WIDTH * N_NEURONS;
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/*
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* Deterministic benchmark vectors.
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*
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* These are INTERNAL signals.
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* They are deliberately marked keep so that Yosys does not
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* constant-fold the complete neural datapath away.
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*/
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(* keep = "true" *)
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wire signed [X_BITS-1:0] x_bus;
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(* keep = "true" *)
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wire signed [W_BITS-1:0] weights_bus;
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(* keep = "true" *)
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wire signed [B_BITS-1:0] bias_bus;
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/*
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* Generate deterministic non-zero INT8 data.
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*
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* Each byte is a different constant. The buses remain internal,
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* so nextpnr sees only the 37 real top-level I/Os.
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*/
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genvar i;
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genvar n;
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generate
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for (i = 0; i < N_INPUTS; i = i + 1) begin : GEN_X
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localparam integer XV =
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((i * 17 + 3) % 31) - 15;
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assign x_bus[
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i*DATA_WIDTH +: DATA_WIDTH
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] = XV;
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end
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for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_WN
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for (i = 0; i < N_INPUTS; i = i + 1) begin : GEN_WI
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localparam integer WV =
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((n * 29 + i * 13 + 5) % 31) - 15;
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assign weights_bus[
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(n*N_INPUTS+i)*DATA_WIDTH
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+: DATA_WIDTH
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] = WV;
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end
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end
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for (n = 0; n < N_NEURONS; n = n + 1) begin : GEN_B
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localparam integer BV =
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((n * 7 + 1) % 9) - 4;
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assign bias_bus[
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n*DATA_WIDTH
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+: DATA_WIDTH
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] = BV;
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end
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endgenerate
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/*
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* Real neural-network layer.
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*/
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(* keep_hierarchy = "true" *)
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layer #(
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) dut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.weights_bus(weights_bus),
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.bias_bus(bias_bus),
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.y_bus(y_bus),
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.busy(busy),
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.done(done)
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);
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endmodule |