micheleandClaude Sonnet 5
eb0b0f9170
Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single authoritative pre-schematic verification record: RTL/ERR-0025/ regression re-verification, clock/reset, synthesis/P&R re-audit, setup/hold timing status, the real SDRAM datasheet-parameter audit table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge protocol documentation, FPGA power/pinout tables, first-board bring-up and benchmark status, and cross-domain consistency audit. Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit, SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) -- this was the one section-11 item the governing mandate required not be left OPEN. Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/ POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they predate the SPI host bridge, PLL, and this session's SDRAM datasheet audit) with pointers to the new consolidated document, rather than rewriting each individually. Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the SDRAM datasheet audit and configuration-flash decisions, rebuilds the PDF (clean compile, 16 pages). Classification: PRE-PCB VERIFIED. Schematic and PCB implementation remain user-owned and not started. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
119 lines
6.4 KiB
Markdown
119 lines
6.4 KiB
Markdown
# FPGA-Neural V2 — OPEN ITEMS
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**SUPERSEDED.** See `PRE_PCB_VERIFICATION.md`'s own final release-gate
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table for the current, consolidated OPEN/PASS status of every item
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below — most of the BLOCKER/CRITICAL items here (host interface,
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clock/PLL, pinout) are now CLOSED. Left in place as a historical
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record.
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Consolidated from HARDWARE_FREEZE.md, PINOUT.md, CLOCK_ARCHITECTURE.md,
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POWER_ARCHITECTURE.md, SCHEMATIC_READINESS.md. Classified per the
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governing spec's own rule: BLOCKER / CRITICAL / WARNING / OPEN /
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FUTURE.
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## BLOCKER (impede la realizzazione o il funzionamento del chip)
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0. **RESOLVED (STEP20).** A real SPI host interface (`spi_host_bridge.v`)
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is now implemented, protocol-correct in isolation (18/18,
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`tb_spi_host_bridge.v`), AND verified correct end-to-end through the
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full SPI→dependency_manager→compute→SDRAM→result path under both
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tight and realistic (widely time-separated) job pacing (11/11,
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`tb_fpga_neural_v2_top_smoke.v`) — see errors.log's own "ERR-0025
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Part B — RESOLUTION" entry for the full root-cause writeup (a
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registered- vs combinational-read latency mismatch in the shared
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weight/activation SRAMs, fixed with zero regression to the STEP19
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baseline). This item is CLOSED — kept here only for the historical
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record; item 1 below is likewise no longer a real blocker in the
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sense of "the RTL doesn't exist" — it remains open only for real
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pinout/board-connector work (see item 1's own updated text).
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1. **RESOLVED (STEP20).** The RTL's own internal "host" ports (`reg_valid`
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/`reg_node_id`/`reg_required`/`reg_producer_ids`/`reg_x_base`/
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`reg_w_base`/`reg_n_tiles`/`reg_result_addr`) remain a simulation/
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testbench-only bus for `nms_neural_multiprocessor_sdram_unified.v`
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in isolation, but the board-level top (`fpga_neural_v2_top.v`) now
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drives these SAME internal ports from `spi_host_bridge.v`, a real,
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verified SPI protocol engine (WRITE_JOB/WRITE_MEM/READ_MEM/STATUS/
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RESET), matching V1's own `spi_neuron_top.v` precedent. The 110-pin
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bus is no longer exposed as a physical top-level port at all in
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`fpga_neural_v2_top.v` — only 4 real SPI pins (sclk/mosi/miso/cs_n)
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are.
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2. **The 110-pin host/registration bus has no real ball assignment** —
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moot now (see item 1): it is an internal signal, not a top-level
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port, in the board-level top. The 4 real SPI pins likewise have no
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ball assignment yet, since `fpga_neural_v2_top.v` has not been
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through P&R this round (see the next open item). The SDRAM bus (37
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signals) and clk/rst (2 signals) now DO have a
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real, sourced, P&R-verified assignment (`hardware/v2/constraints/
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v2_unified.lpf`, from the real Lattice pinout CSV found at
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`~/Downloads/FPGA-SC-02034-3-0-ECP5U-45-Pinout.csv` during this
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step's own pre-commit review) — this item is narrower than
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originally scoped.
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3. **No schematic exists; no PCB has been started.**
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## CRITICAL (rischio elevato, deve essere risolto prima del freeze)
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1. **Timing closure is MARGINAL, with an unfavorable pass rate.** 8
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real P&R seeds for the frozen N=4 single-SDRAM design: only 1/8
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reach ≥80MHz (66.97–81.84MHz range). This is WORSE than STEP18's
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own dual-memory design (5/8 pass). The critical path itself is
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unchanged (still `dependency_manager.v`'s own pre-existing
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`first_ready_idx`/`reg_ready` chain) — the regression is attributed
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to added overall die/routing pressure from consolidation, not a new
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RTL defect, but it is real and unresolved.
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2. **Clock source/oscillator gap -- PARTIALLY ADDRESSED (STEP20).** A
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real EHXPLLL wrapper (`ecp5_pll_sys_clk.v`, real Project Trellis
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`ecppll`-generated parameters, 16MHz->64MHz) now exists and is
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instantiated in `fpga_neural_v2_top.v`. NOT YET confirmed by real
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synthesis/P&R of that board-level top this round (deliberately
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deferred until ERR-0025 Part B was resolved -- see decisions.log
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DEC-0037) -- this is the immediate next real step. Prior project memory
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records a 16MHz board oscillator. Neither "source an 80MHz+
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oscillator" nor "add a real PLL to the RTL" has been decided.
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3. **Two physical memories were required through STEP18** — RESOLVED
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this round (DEC-0034): the V2 physical path no longer instantiates
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`hardware/v1/rtl/psram_controller.v` at all. Kept here only as a
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closed CRITICAL item for the historical record.
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## WARNING (non blocca il prototipo ma deve essere documentato)
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1. N=2's real Fmax (86.04MHz in STEP18's own dual-memory design) and
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the STEP19 single-SDRAM N=2 config were not both measured with the
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same best-of-N-seed rigor as N=4 — a real, disclosed gap in
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measurement thoroughness, not a functional issue.
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2. `W_ENTRIES`/cache sizing in the weight-fetch path was set to match
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`N_SLOTS` (4) by construction reasoning, not swept for optimality.
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3. I/O standard (LVCMOS33 assumed for all 149 signals) has not been
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verified per real VCCIO bank once ball assignment becomes possible.
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## OPEN (decisione ancora da prendere)
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1. Configuration-flash part number / SPI-flash-boot vs JTAG-only
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bring-up.
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2. Power regulator topology and part numbers (the previously-recorded
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`../basic-ecp5-pcb` reference design is not accessible this
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session to confirm as a concrete plan).
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3. Real current budget (requires running a real power-estimation tool
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against the actual synthesized netlist — not done this round).
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4. Decoupling/bulk capacitance values (depend on regulator selection).
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5. Reset synchronization to a real external POR/supervisor source.
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6. Real per-bank VCCIO/I-O-standard verification once ball data is
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available.
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## FUTURE EVOLUTION (miglioramento post-freeze — explicitly deferred)
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1. N=8 evaluation.
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2. A smarter W/AR priority scheme in `sdram_unified_backend.v` to
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recover some of the +10.8% (N=4) / +5.1% (N=2) cycle-count cost of
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single-SDRAM unification (STEP18 EXP-0046's own packing win is
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still present — this is about the NEW W-vs-AR contention specifically).
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generic
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3. Page-mode / keep-row-open SDRAM controller redesign (STEP18's own
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identified next bottleneck for raw memory bandwidth, independent of
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the single-vs-dual-memory question).
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4. True multi-outstanding SDRAM request pipelining (STEP18 Part E's
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own documented, deliberately out-of-scope boundary).
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5. A real physical host-interface RTL bridge (SPI or similar),
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resolving BLOCKER #1 above.
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6. Floorplanning / seed-pinning work to convert the current MARGINAL
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timing result into a reliable PASS.
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