FPGA-Neural

Files

T

micheleandClaude Sonnet 5 786464ee21 feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

Closes part of the gap found re-auditing spi_host_bridge.v against V3:
V3 had no host raw-memory-access path into DDR3 at all. This module
translates single-16-bit-word req/wr/addr/wdata/lb_n/ub_n transactions
(spi_host_bridge.v's own WRITE_MEM/READ_MEM shape) into BURST_LEN=8
transactions on the shared arbiter, using the project's existing
DQM-style partial-burst masking technique.

Verified standalone against the SDR SDRAM placeholder: 16/16 tests,
0 errors, including cross-word-corruption checks on every burst
offset. Not yet wired into the N=2 system or driven by real SPI
opcode decode.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-17 08:53:23 +02:00

host_mem_bridge.v

feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

2026-09-17 08:53:23 +02:00

mac2_dsp_packed.v

v3: real Artix-7 compute core -- DSP48 packing verified, 2 real bugs found and fixed

2026-09-16 19:48:46 +02:00

mig_native_adapter.v

feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

2026-09-17 08:43:22 +02:00

n2_system_top.v

exp: real P&R of the N=2 multi-core system, first genuine system Fmax (EXP-0067)