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micheleandClaude Sonnet 5 786464ee21 feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

Closes part of the gap found re-auditing spi_host_bridge.v against V3:
V3 had no host raw-memory-access path into DDR3 at all. This module
translates single-16-bit-word req/wr/addr/wdata/lb_n/ub_n transactions
(spi_host_bridge.v's own WRITE_MEM/READ_MEM shape) into BURST_LEN=8
transactions on the shared arbiter, using the project's existing
DQM-style partial-burst masking technique.

Verified standalone against the SDR SDRAM placeholder: 16/16 tests,
0 errors, including cross-word-corruption checks on every burst
offset. Not yet wired into the N=2 system or driven by real SPI
opcode decode.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-17 08:53:23 +02:00

architecture.log

V2.0.0 hardware freeze - single SDRAM

2026-09-06 13:39:55 +02:00

benchmark.log

perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)

2026-09-05 20:59:14 +02:00

decisions.log

docs: log DEC-0009 -- project v22 paused, hard DSP resource ceiling on ECP5

2026-09-16 15:38:39 +02:00

development.log

V2.0.0 hardware freeze - single SDRAM

2026-09-06 13:39:55 +02:00

errors.log

docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

2026-09-15 20:28:16 +00:00

experiments.log

feat: host_mem_bridge.v, word<->burst translator for host DDR3 access (EXP-0071)

2026-09-17 08:53:23 +02:00

README.md

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

simulation.log

perf(v2): shared activation cache - further 1.66-2.00x real speedup (DEC-0016)

2026-09-05 20:59:14 +02:00

synthesis.log

docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

2026-09-15 20:28:16 +00:00

timing.log

docs+synth: Phase 0 complete - N=8 baseline + toolchain discrepancy closed

2026-09-15 21:44:10 +00:00

README.md

Formato dei log V2

Regola non negoziabile (docs/v2-description.md §25-29): ogni attività significativa (modifica, simulazione, sintesi, benchmark, decisione, errore) deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai riutilizzato, anche se il risultato è un FAIL.

File

development.log — log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).
architecture.log — decisioni e note di architettura a grana fine (non scelte finali — quelle vanno in decisions.log — ma esplorazioni, alternative considerate, vincoli scoperti).
simulation.log — ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.
synthesis.log — ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.
timing.log — ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.
benchmark.log — tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.
decisions.log — decisioni architetturali importanti, formato DEC-XXXX (vedi docs/v2-description.md §27).
experiments.log — registro principale, un EXP-XXXX per ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda a reports/experiments/EXP-XXXX/.
errors.log — errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi in hardware/v1/docs/validation/bugs.md).

Campi minimi per entry (§26)

timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action

Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.