FPGA-Neural

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micheleandClaude Sonnet 5 78577dde59 docs: log real Vivado stale-source bug + final flash-bridge P&R signoff (EXP-0078)

Found and fixed a real Vivado project-management bug: two source
files (n2_system_ddr3_top.v, spi_host_bridge_v3.v) had stale imported
copies (plus a duplicate at a second path) that silently kept being
used in synth+impl despite live edits, making the first "flash bridge
included" P&R run silently synthesize the OLD design (STARTUPE2
Used=0/1 gave it away). Fixed by removing the stale/duplicate entries
and re-adding both files as direct (non-copied) references.

Final real P&R: STARTUPE2 Used=1/1 (confirms the flash bridge is
genuinely placed/routed), timing still closes but margin is now
thinner and real: WNS +0.013ns, WHS +0.032ns, 0 failing endpoints.
5213 LUTs, 16 DSP48E1.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 07:24:33 +02:00

constraints

docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

2026-09-15 20:28:16 +00:00

ddr3

exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

2026-09-16 12:01:11 +02:00

docs

docs: extract V2 datasheet into submodule

2026-09-16 23:03:43 +02:00

logs

docs: log real Vivado stale-source bug + final flash-bridge P&R signoff (EXP-0078)