FPGA-Neural

T

micheleandClaude Sonnet 5 77e74db637 docs: final certification verdict for the re-certification campaign

Consolidates Fase 0 + C.1-C.14 + D into one verdict: the project is
NOT certifiable without reservations as a whole. Core arithmetic
datapath is solid (exhaustively certified where possible); control/
sequencing/arbitration is correct on the happy path (40 real tests
pass via an independent regression harness). 7 real bugs found, all
traceable to one systemic pattern (unguarded "real=0" boundary values
plus one unguarded mid-run configuration write). 2 of 7 are CRITICAL
(BUG-005, BUG-007), reachable via documented SPI opcodes under
plausible conditions, with real PSRAM corruption or inference-hang
risk. None were documented before this campaign.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-04 19:59:58 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: final certification verdict for the re-certification campaign

2026-09-04 19:59:58 +02:00

rtl

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

2026-09-04 10:16:31 +02:00

sim

test: certify spi_neuron_top mux/pins (C.8), find critical BUG-007