23 lines
556 B
Verilog
23 lines
556 B
Verilog
module mac_unit #(
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parameter DATA_WIDTH = 16,
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parameter ACC_WIDTH = 40
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)(
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input signed [DATA_WIDTH-1:0] x,
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input signed [DATA_WIDTH-1:0] w,
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input signed [ACC_WIDTH-1:0] acc_in,
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output signed [ACC_WIDTH-1:0] acc_out
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);
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localparam PROD_WIDTH = 2 * DATA_WIDTH;
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wire signed [PROD_WIDTH-1:0] product;
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wire signed [ACC_WIDTH-1:0] product_ext;
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assign product = x * w;
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assign product_ext =
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{{(ACC_WIDTH-PROD_WIDTH){product[PROD_WIDTH-1]}}, product};
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assign acc_out = acc_in + product_ext;
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endmodule |