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FPGA-Neural/hardware/v2/synthesis/harness_memory_manager/nextpnr.log
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micheleandClaude Sonnet 5 175f697ae1 feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend 
Implements M4: memory_manager.v (arbitration/buffering/forwarding/
latency hiding/double buffering, §12) + prefetch_engine.v
(double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1
PSRAM backend chain (int8_memory_access.v -> memory_interface.v ->
psram_controller.v, per §15's explicit mandate not to touch the
controller).

Verified fully end-to-end with Verilator: real neural_processor (M1)
fed entirely by memory_manager, computing against PSRAM-resident X/W
tiles (double-buffered prefetch across up to 5 tiles) and writing its
result back to PSRAM -- checked via an independent PSRAM read-back,
with poison bytes around the operand regions to catch addressing
errors. 3/3 jobs pass (1/3/5-tile configurations).

Three real RTL bugs found and fixed during integration (full
diagnostic trail in errors.log ERR-0006): prefetch_engine had no
single-in-flight-request discipline, letting a queued request corrupt
the bank bookkeeping of a fetch already running; the fix's own
!pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a
clock) that needed an explicit !pf_start term; and a state-based mux
for the shared backend port was off by one cycle, silently dropping
the PSRAM result write entirely.

Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP
(expected, no multiplication in this module). Real place&route (via a
synthesis-only timing harness, needed for the same TRELLIS_IO pin-
budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:39:29 +02:00

303 lines
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Info: Logic utilisation before packing:
Info: Total LUT4s: 349/43848 0%
Info: logic LUTs: 257/43848 0%
Info: carry LUTs: 92/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 203/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 72 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x6e129573
Info: Device utilisation:
Info: TRELLIS_IO: 18/ 245 7%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 203/ 43848 0%
Info: TRELLIS_COMB: 383/ 43848 0%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 333 cells, random placement wirelen = 28028.
Info: at initial placer iter 0, wirelen = 1283
Info: at initial placer iter 1, wirelen = 1162
Info: at initial placer iter 2, wirelen = 1104
Info: at initial placer iter 3, wirelen = 1098
Info: Running main analytical placer, max placement attempts per cell = 45753.
Info: at iteration #1, type ALL: wirelen solved = 1068, spread = 2127, legal = 2276; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1116, spread = 2137, legal = 2271; time = 0.01s
Info: at iteration #3, type ALL: wirelen solved = 1148, spread = 1979, legal = 2159; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 1209, spread = 1880, legal = 2056; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 1233, spread = 1999, legal = 2152; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 1282, spread = 1933, legal = 2171; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 1355, spread = 1921, legal = 2143; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 1411, spread = 1875, legal = 2071; time = 0.00s
Info: at iteration #9, type ALL: wirelen solved = 1399, spread = 1911, legal = 2120; time = 0.00s
Info: HeAP Placer Time: 0.07s
Info: of which solving equations: 0.04s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 91, wirelen = 2056
Info: at iteration #5: temp = 0.000000, timing cost = 72, wirelen = 1619
Info: at iteration #10: temp = 0.000000, timing cost = 93, wirelen = 1531
Info: at iteration #15: temp = 0.000000, timing cost = 90, wirelen = 1514
Info: at iteration #15: temp = 0.000000, timing cost = 89, wirelen = 1514
Info: SA placement time 0.09s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 164.28 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.99 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.67 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6413, 6680) |*********
Info: [ 6680, 6947) |*****
Info: [ 6947, 7214) |****
Info: [ 7214, 7481) |********
Info: [ 7481, 7748) |***
Info: [ 7748, 8015) |
Info: [ 8015, 8282) |**
Info: [ 8282, 8549) |********
Info: [ 8549, 8816) |*******
Info: [ 8816, 9083) |*************
Info: [ 9083, 9350) |***************************************
Info: [ 9350, 9617) |****************************
Info: [ 9617, 9884) |*********************
Info: [ 9884, 10151) |*******************************
Info: [ 10151, 10418) |**************************
Info: [ 10418, 10685) |********************************
Info: [ 10685, 10952) |**********
Info: [ 10952, 11219) |*******************
Info: [ 11219, 11486) |*********************************************
Info: [ 11486, 11753) |***************************************
Info: Checksum: 0x691562ea
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1629 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 209 742 | 209 742 | 884| 0.08 0.08|
Info: 2000 | 361 1528 | 152 786 | 65| 0.13 0.21|
Info: 2066 | 363 1587 | 2 59 | 0| 0.01 0.22|
Info: Routing complete.
Info: Router1 time 0.22s
Info: Checksum: 0x5e42e5ef
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source dut.tile_idx_TRELLIS_FF_Q_2.Q
Info: routing 0.93 1.32 Net dut.tile_idx[3] (31,5) -> (32,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:90.26-90.34
Info: logic 0.35 1.68 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 1.68 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,2) -> (32,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 1.68 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 1.68 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,2) -> (32,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.54
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 1.73 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 1.73 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,2) -> (32,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 1.73 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 1.73 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.54
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 1.79 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 1.79 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 1.79 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 1.79 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.54
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 1.84 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 1.84 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 1.84 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 1.84 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.54
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 1.90 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 1.90 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 1.90 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 1.90 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN (33,2) -> (33,2)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.54
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 2.23 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1$CCU2_COMB0.F
Info: routing 1.01 3.24 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_S0 (33,2) -> (34,3)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A
Info: logic 0.35 3.60 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 3.60 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN (34,3) -> (35,3)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: hardware/v2/rtl/memory_manager.v:255.38-255.68
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 3.65 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 3.65 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_FCI_INT (35,3) -> (35,3)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 3.65 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 3.65 Net $nextpnr_CCU2C_5$CIN (35,3) -> (35,3)
Info: Sink $nextpnr_CCU2C_5$CCU2_COMB0.FCI
Info: logic 0.33 3.98 Source $nextpnr_CCU2C_5$CCU2_COMB0.F
Info: routing 0.71 4.69 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z[2] (35,3) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.87 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 4.87 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32
Info: logic 0.13 5.00 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 5.00 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1 (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56
Info: logic 0.18 5.18 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 5.18 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0 (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68
Info: logic 0.18 5.36 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.67 6.03 Net dut.pf_pending_x_TRELLIS_FF_Q_CE (35,4) -> (35,7)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_1.CE
Info: setup 0.00 6.03 Source dut.pf_pending_x_TRELLIS_FF_Q_1.CE
Info: 2.71 ns logic, 3.32 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 1.39 1.39 Net rst$TRELLIS_IO_IN (38,0) -> (35,7)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_C_LUT4_Z.B
Info: Defined in:
Info: hardware/v2/synthesis/harness_memory_manager.v:18.17-18.20
Info: logic 0.18 1.57 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_C_LUT4_Z.F
Info: routing 0.92 2.49 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C[2] (35,7) -> (36,4)
Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.67 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A.F
Info: routing 0.49 3.16 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z[3] (36,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.34 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 3.34 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48
Info: logic 0.13 3.47 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 3.47 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1 (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64
Info: logic 0.18 3.65 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 3.65 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1 (35,4) -> (35,4)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 3.83 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.67 4.50 Net dut.pf_pending_x_TRELLIS_FF_Q_CE (35,4) -> (35,7)
Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_1.CE
Info: setup 0.00 4.50 Source dut.pf_pending_x_TRELLIS_FF_Q_1.CE
Info: 1.03 ns logic, 3.47 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q
Info: routing 2.91 3.30 Net checksum[2]$TRELLIS_IO_OUT (38,8) -> (90,11)
Info: Sink checksum[2]$tr_io.I
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: 0.40 ns logic, 2.91 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 165.86 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.50 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.30 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 6471, 6738) |*******
Info: [ 6738, 7005) |**
Info: [ 7005, 7272) |**
Info: [ 7272, 7539) |*
Info: [ 7539, 7806) |*
Info: [ 7806, 8073) |***
Info: [ 8073, 8340) |*************
Info: [ 8340, 8607) |***
Info: [ 8607, 8874) |****
Info: [ 8874, 9141) |*************
Info: [ 9141, 9408) |**********************************************
Info: [ 9408, 9675) |***********************************
Info: [ 9675, 9942) |**************************
Info: [ 9942, 10209) |******************************
Info: [ 10209, 10476) |****************************
Info: [ 10476, 10743) |****************
Info: [ 10743, 11010) |**************
Info: [ 11010, 11277) |*********************
Info: [ 11277, 11544) |**********************************************
Info: [ 11544, 11811) |**************************************
Info: Program finished normally.
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