micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
211 lines
8.7 KiB
Verilog
211 lines
8.7 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// M2 testbench (docs/v2-description.md §8/§18/§34): neural_processor_array.v
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// with N_PROCESSORS=4. Verified with Verilator (see hardware/v2/logs/
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// decisions.log DEC-0004 -- Icarus Verilog v13.0 is not trusted for
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// hardware/v2 testbenches).
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//
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// Coverage:
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// - TEST 1: single processor (index 0), sanity check that the
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// array's per-processor bus flattening/slicing is wired correctly
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// (arithmetic itself already bit-exact-certified at M1).
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// - TEST 2: all 4 processors launched on the SAME cycle with
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// DIFFERENT jobs (different tile counts, so they finish at
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// different times) -- proves genuine concurrent, independent
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// execution, not a hidden shared resource serializing them.
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// - TEST 3: staggered start (processor 1 launched while processor 0
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// is still mid-job) -- proves a busy processor does not block a
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// job being accepted by another (§18/§34: "un processor bloccato
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// non deve bloccare gli altri").
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// ============================================================
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module tb;
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localparam DATA_WIDTH = 8;
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localparam P_IN = 8;
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localparam ACC_WIDTH = 32;
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localparam N_PROCESSORS = 4;
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reg clk, rst;
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initial begin clk = 0; forever #5 clk = ~clk; end
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reg [N_PROCESSORS-1:0] job_valid;
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wire [N_PROCESSORS-1:0] job_ready;
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reg [16*N_PROCESSORS-1:0] job_node_id;
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reg signed [DATA_WIDTH*N_PROCESSORS-1:0] job_bias;
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reg [2*N_PROCESSORS-1:0] job_activation;
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reg [N_PROCESSORS-1:0] operand_valid;
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wire [N_PROCESSORS-1:0] operand_ready;
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reg signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] input_data;
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reg signed [DATA_WIDTH*P_IN*N_PROCESSORS-1:0] weight_data;
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reg [N_PROCESSORS-1:0] tile_last;
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wire [N_PROCESSORS-1:0] result_valid;
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reg [N_PROCESSORS-1:0] result_ready;
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wire signed [DATA_WIDTH*N_PROCESSORS-1:0] result_data;
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wire [16*N_PROCESSORS-1:0] result_node_id;
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wire [4*N_PROCESSORS-1:0] np_state;
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wire [N_PROCESSORS-1:0] np_error;
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neural_processor_array #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH),
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.N_PROCESSORS(N_PROCESSORS)
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) dut (
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.clk(clk), .rst(rst),
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.job_valid(job_valid), .job_ready(job_ready),
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.job_node_id(job_node_id), .job_bias(job_bias), .job_activation(job_activation),
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.operand_valid(operand_valid), .operand_ready(operand_ready),
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.input_data(input_data), .weight_data(weight_data), .tile_last(tile_last),
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.result_valid(result_valid), .result_ready(result_ready),
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.result_data(result_data), .result_node_id(result_node_id),
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.np_state(np_state), .np_error(np_error)
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);
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integer errors, tests;
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// ---- per-processor job launch task: fires the job handshake and
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// every tile for processor `idx`, WITHOUT waiting for
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// completion (so the caller can launch several processors
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// back-to-back / interleaved and observe true concurrency). ----
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task automatic launch_job(
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input integer idx,
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input integer n_tiles,
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input signed [DATA_WIDTH-1:0] lane_x,
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input signed [DATA_WIDTH-1:0] lane_w,
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input signed [DATA_WIDTH-1:0] bias,
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input [1:0] activation,
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input [15:0] node_id
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);
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integer t, k;
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reg signed [DATA_WIDTH*P_IN-1:0] tile_data;
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begin
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@(posedge clk);
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job_node_id[idx*16 +: 16] = node_id;
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job_bias[idx*DATA_WIDTH +: DATA_WIDTH] = bias;
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job_activation[idx*2 +: 2] = activation;
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job_valid[idx] = 1'b1;
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while (!job_ready[idx]) @(posedge clk);
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@(posedge clk);
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job_valid[idx] = 1'b0;
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tile_data = {DATA_WIDTH*P_IN{1'b0}};
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for (k = 0; k < P_IN; k = k + 1)
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tile_data[k*DATA_WIDTH +: DATA_WIDTH] = lane_x;
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for (t = 0; t < n_tiles; t = t + 1) begin
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input_data[idx*DATA_WIDTH*P_IN +: DATA_WIDTH*P_IN] = tile_data;
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for (k = 0; k < P_IN; k = k + 1)
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weight_data[idx*DATA_WIDTH*P_IN + k*DATA_WIDTH +: DATA_WIDTH] = lane_w;
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tile_last[idx] = (t == n_tiles - 1);
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operand_valid[idx] = 1'b1;
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while (!operand_ready[idx]) @(posedge clk);
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@(posedge clk);
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end
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operand_valid[idx] = 1'b0;
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tile_last[idx] = 1'b0;
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end
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endtask
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// ---- wait for processor `idx` to produce a result, check it,
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// then let it fully return to idle. ----
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task automatic collect_result(
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input integer idx,
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input signed [DATA_WIDTH-1:0] expect_y,
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input [15:0] expect_node_id
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);
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integer wd;
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reg signed [DATA_WIDTH-1:0] got_y;
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reg [15:0] got_node;
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begin
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tests = tests + 1;
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result_ready[idx] = 1'b1;
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wd = 0;
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while (!result_valid[idx] && wd < 300) begin
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@(posedge clk);
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wd = wd + 1;
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end
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if (!result_valid[idx]) begin
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$display("FAIL proc=%0d: no result_valid within watchdog", idx);
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errors = errors + 1;
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end else begin
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got_y = result_data[idx*DATA_WIDTH +: DATA_WIDTH];
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got_node = result_node_id[idx*16 +: 16];
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@(posedge clk);
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if (got_y !== expect_y || got_node !== expect_node_id) begin
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$display("FAIL proc=%0d: got y=%0d node=%0d, expected y=%0d node=%0d",
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idx, got_y, got_node, expect_y, expect_node_id);
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errors = errors + 1;
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end else begin
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$display("PASS proc=%0d: y=%0d node=%0d", idx, got_y, got_node);
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end
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end
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while (!job_ready[idx]) @(posedge clk);
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end
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endtask
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integer i;
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initial begin
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errors = 0;
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tests = 0;
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rst = 1;
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job_valid = 0; job_node_id = 0; job_bias = 0; job_activation = 0;
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operand_valid = 0; input_data = 0; weight_data = 0; tile_last = 0;
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result_ready = 0;
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repeat(4) @(posedge clk);
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rst = 0;
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@(posedge clk);
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// ---- TEST 1: single processor (idx 0), 2 tiles, ACT_RELU ----
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// 16 inputs of x=3,w=2 -> acc=96, bias=0, relu(96)=96
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launch_job(0, 2, 8'sd3, 8'sd2, 8'sd0, 2'd1, 16'd101);
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collect_result(0, 8'sd96, 16'd101);
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// ---- TEST 2: all 4 processors launched the SAME cycle,
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// different tile counts (1,2,3,4) so they finish at different
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// times -- proves genuine independent concurrent execution. ----
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fork
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launch_job(0, 1, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd200); // sum=8
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launch_job(1, 2, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd201); // sum=16
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launch_job(2, 3, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd202); // sum=24
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launch_job(3, 4, 8'sd1, 8'sd1, 8'sd0, 2'd1, 16'd203); // sum=32
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join
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fork
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collect_result(0, 8'sd8, 16'd200);
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collect_result(1, 8'sd16, 16'd201);
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collect_result(2, 8'sd24, 16'd202);
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collect_result(3, 8'sd32, 16'd203);
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join
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// ---- TEST 3: staggered start -- processor 0 launched first
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// with a long (6-tile) job, processor 1 launched a few cycles
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// later while processor 0 is still mid-job. Both must
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// complete correctly and independently. ----
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fork
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begin
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launch_job(0, 6, 8'sd2, 8'sd2, 8'sd0, 2'd1, 16'd300); // sum=8*6*... wait per-tile sum=8*4=32*6=192->sat 127
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end
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begin
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repeat(3) @(posedge clk); // let processor 0 get well underway first
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launch_job(1, 1, 8'sd5, 8'sd5, 8'sd0, 2'd0, 16'd301); // sum=8*25=200, ACT_NONE saturates to 127
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end
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join
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fork
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collect_result(0, 8'sd127, 16'd300); // 8 lanes * 2*2=4 -> 32/tile *6 tiles=192, ACT_RELU saturate +127
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collect_result(1, 8'sd127, 16'd301); // 8 lanes * 5*5=25 -> 200, ACT_NONE saturate +127
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join
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$display("========================================");
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if (errors == 0)
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$display("ALL %0d TESTS PASSED (N_PROCESSORS=%0d array, concurrent/staggered/independent)", tests, N_PROCESSORS);
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else
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$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
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$display("========================================");
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$finish;
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end
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endmodule
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