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micheleandClaude Sonnet 5 dc0b331d3e feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

Begins the V2 Neural Multiprocessor / Dataflow architecture per
docs/v2-description.md, per explicit user request to freeze V1 and
start V2 development, copying from V1 what's needed.

Scaffold:
- hardware/v1/: byte-exact, read-only copy of the current V1 codebase
  (rtl, testbenches, tools, constraints, a representative subset of
  synthesis results, and reference docs) -- verified identical via
  diff/cmp against the live top-level tree before being made
  filesystem-read-only. The live top-level tree is untouched and
  remains the project's "production" V1 (see hardware/v1/README.md
  and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move).
- hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/
  reports/scripts/logs/docs) plus the full logging system required by
  the spec (development/architecture/simulation/synthesis/timing/
  benchmark/decisions/experiments/errors.log).

M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v):
- 8-stage pipelined perceptron unit (P_IN=8): input align, 8
  multipliers, 3-level adder tree, accumulator, bias+activation, INT8
  saturation. Genuine 1-tile/cycle throughput, not just a wider
  combinational datapath.
- 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with
  4 baseline states merged into NP_WAIT_OPERANDS -- see
  decisions.log DEC-0002); valid/ready/data/last stream interfaces
  per §7.
- Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v
  + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v),
  covering regular/mixed-sign/extreme-INT8 vectors, both activations,
  a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile
  job -- verified with Verilator (see below for why).
- Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK
  problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's
  isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24
  (a user-requested comparison experiment, also bit-exact-verified;
  see experiments.log EXP-0001/EXP-0002 and benchmark.log).

Three real bugs found and resolved during M1 development (full
diagnostic record in errors.log):
- Two independent, reproducible Icarus Verilog v13.0 scheduling
  defects (ERR-0001, ERR-0002) that silently produced wrong simulation
  results for standard sequential Verilog -- confirmed via Verilator
  5.050 giving correct results on the same minimal repros. Verilator
  is now the trusted simulator for hardware/v2/ (decisions.log
  DEC-0004); Icarus's affected protocol-violation check was removed
  from the RTL and deferred architecturally to the Neural Director
  (DEC-0003) rather than chased further.
- One real RTL bug (ERR-0003): last0 wasn't gated like valid0,
  letting a "last tile" tag leak into the pipeline ahead of its
  actual valid tile on back-to-back jobs. Fixed and verified.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-05 14:06:53 +02:00

constraints

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

docs

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

rtl

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

sim

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

synthesis

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

tools

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

README.md

feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor

2026-09-05 14:06:53 +02:00

README.md

FPGA-Neural V1 — Golden Reference (FROZEN)

Questo albero è una copia bit-esatta del codice V1 così come esisteva al commit 07a48e4 (fix: close 7 zero-value/mid-run guard gaps found in re-certification campaign) del repository principale. Verificato byte-per-byte al momento della creazione (diff -rq contro rtl/ e sim/*.v dell'albero principale, 0 differenze).

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Questo albero non deve mai essere modificato. È il riferimento funzionale, numerico, prestazionale e bit-exact per ogni sviluppo V2 (hardware/v2/), per policy esplicita di docs/v2-description.md §1 e §34 ("V1 rimane intatta").

Se un bug o miglioramento V1 viene scoperto durante lo sviluppo V2, non correggerlo qui: documentarlo in hardware/v2/logs/decisions.log o errors.log e, se necessario, applicarlo separatamente al V1 "vivo" nell'albero principale del repository (rtl/, sim/, ecc.), mai in questa copia.

Contenuto

rtl/ — i 20 moduli RTL V1 (copia di rtl/*.v dell'albero principale).
sim/ — le 47 testbench V1 (copia di sim/*.v, esclusi i .vcd generati: rieseguibili in loco con iverilog/vvp, non servono duplicati).
tools/ — copia di tools/ (harness di regressione, netasm, generatore .lpf, oracoli di validazione).
constraints/ — i vincoli .lpf per ECP5 (spi_neuron_top.lpf, spi_neuron_top_flash.lpf).
synthesis/ — sottoinsieme rappresentativo dei risultati di sintesi reale già misurati sul V1 (non l'intera storia sperimentale, che resta nell'albero principale sotto synth/ecp5/):
- post_fix_verify/ — sistema completo (spi_neuron_top con sottosistema flash, PARALLEL=8), stato più recente e autorevole: 0 errori di vincolo, Fmax 68.65 MHz.
- p2/, p4/, p8/ — sweep isolato di neuron_parallel a PARALLEL variabile (N_INPUTS=256), stessa fonte dei numeri citati in docs/v2-description.md §3 per P8/P4/P2. Il dato P16 (52.13 MHz) citato nella stessa sezione proviene da docs/FPGA-Neural-Datapatch-Benchmark.md (copiato in docs/), non da un artefatto di sintesi grezzo separato.
docs/ — copia dei documenti di riferimento: WORKLOG.md, i capitoli di docs/validation/ (campagna di certificazione + registro bug), il datasheet markdown (FPGA-NeuralNetwork-Engine.md), il report benchmark (FPGA-Neural-Datapatch-Benchmark.md) e il documento hardware (FPGA-Neural-Hardware-Design.md).

Dati baseline citati da V2 (`docs/v2-description.md` §3)

Config	Fmax (isolato, N_INPUTS=256)	Fonte
PARALLEL=16	52.13 MHz (FAIL @80MHz)	`docs/FPGA-Neural-Datapatch-Benchmark.md`
PARALLEL=8	61.71 MHz (FAIL @80MHz)	`synthesis/p8/`
PARALLEL=4	75.01 MHz (FAIL @80MHz)	`synthesis/p4/`
PARALLEL=2	87.88 MHz (PASS @80MHz)	`synthesis/p2/`

Sistema integrato (spi_neuron_top, PARALLEL=8, sottosistema flash incluso): 68.65 MHz (synthesis/post_fix_verify/, più recente della cifra 65.13 MHz citata in docs/v2-description.md §3, che si riferiva a uno stato pre-fix precedente — vedi docs/WORKLOG.md per la cronologia completa).

Percorso critico osservato in ogni misura: logica di neuron_parallel.v (catena di riporto CCU2C del comparatore/accumulatore) e la sua interconnessione — mai il controller PSRAM.

README.md

FPGA-Neural V1 — Golden Reference (FROZEN)

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Contenuto

Dati baseline citati da V2 (docs/v2-description.md §3)

Dati baseline citati da V2 (`docs/v2-description.md` §3)