FPGA-Neural

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micheleandClaude Sonnet 5 6d06404428 feat: real N=4/N=8 timing curve -- N=8 REALLY CLOSES (0 failing endpoints, EXP-0095)

Fixed a real, previously-untested N_GROUPS=1 edge case in
neural_director_grouped.v (bare $clog2(N_GROUPS) invalid for
N_GROUPS=1, same class of bug sdram_arbiter_n.v's own SELW guard
already handles -- applied the same fix here and in
n16_system_ddr3_top.v's own job_out_group_w wire).

Real synth_design -generic N_GROUPS=<n> P&R sweep (same RTL/arbiter as
EXP-0094's real N=16 result):
  N=4  (N_GROUPS=1): WNS=-0.005ns, 2 failing endpoints
  N=8  (N_GROUPS=2): WNS=0.000ns, 0 failing endpoints -- REALLY CLOSED
  N=16 (N_GROUPS=4): WNS=-0.338ns, 60 failing endpoints (EXP-0094)

N=8 is a real, new, closed P&R signoff -- 8x N=2's parallelism with
the same already-verified systolic RTL. Answers the user's own
question directly: the design does not fail until somewhere between
N=8 and N=16, not at N=4 or N=8.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-21 07:56:19 +02:00

constraints

docs+synth: Phase 0 baseline (N_SLOTS=4, real board top), fix stale LPF freq

2026-09-15 20:28:16 +00:00

ddr3

exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

2026-09-16 12:01:11 +02:00

docs

docs: extract V2 datasheet into submodule

2026-09-16 23:03:43 +02:00

logs

feat: real N=4/N=8 timing curve -- N=8 REALLY CLOSES (0 failing endpoints, EXP-0095)