micheleandClaude Sonnet 5
6cff2c8a7c
neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around the real, unmodified V1 PSRAM backend chain (int8_memory_access -> memory_interface -> psram_controller), funneling N_SLOTS independent Memory Backend Interface ports through a new generic N-port arbiter (slot_mem_arbiter.v) inspired by (not copied from) V1's own mem_arbiter.v. Real concurrent-slot simulation immediately surfaced a genuine bug (ERR-0008): memory_manager/prefetch_engine's byte-level backend protocol is fire-and-forget (a single-cycle mem_req pulse with no accept handshake) - correct for M4's direct 1:1 connection, but a naive arbiter silently drops a pulse arriving while the shared bus is owned by another slot, hanging that slot forever. Fixed with a per-port pending-request latch, the same "queue, don't drop" idiom already used by memory_manager's own pf_pending register (ERR-0006). Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for one real PSRAM port (444 cycles). No regression on M4's own testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45 MHz, PASS at 80MHz. Arbitration policy is fixed lowest-index priority, not fairness- balanced (DEC-0010) - consistent with every other "simplest correct policy first" scheduling choice in this roadmap, revisited only if M9's real measurement shows starvation matters. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/ experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
79 lines
4.3 KiB
Plaintext
79 lines
4.3 KiB
Plaintext
# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
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LUT: 55 FF: 533 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 96
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CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
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neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
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a synthesizable for-loop index in stage 0's unrolled always block,
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not a real multi-driver conflict (cross-verified functionally
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correct on 2 independent simulators). Log: hardware/v2/synthesis/
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neural_processor_p8/yosys.log
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[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
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LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
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CHECK: 0 problems, same 36 benign warnings as EXP-0001.
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Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
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[2026-09-05] EXP-0003 -- neural_processor_array via
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harness_neural_processor_array.v (synthesis-only wrapper, see
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errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
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N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
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N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
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N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
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N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
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CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
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N confirms no unintended cross-processor resource sharing (a first,
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flawed harness attempt fed identical data to every processor/lane
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and Yosys silently deduplicated down to 1x regardless of N -- caught
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by checking for exactly this linearity before trusting the numbers).
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[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
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2 depths each
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activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
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result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
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CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
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fallback). weight_buffer's DP16KD count does NOT drop with depth
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(width-bound, not depth-bound -- see decisions.log / benchmark.log).
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[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone)
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LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no
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multiplication in this module). CHECK: 0 problems.
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[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
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LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
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LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
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[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
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harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
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is needed: bare per-slot Memory Backend Interface ports alone total
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280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
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budget)
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N_SLOTS=2: LUT4=2127 CCU2C=248 TRELLIS_FF=2505 MULT18X18D=16 DP16KD=0
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N_SLOTS=4: LUT4=3953 CCU2C=500 TRELLIS_FF=4688 MULT18X18D=32 DP16KD=0
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CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
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drivers for ...neural_processor.\gi" warnings per neural_processor
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instance already documented in EXP-0001 -- an `integer` for-loop
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index shared across two of neural_processor's own always blocks, not
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a real multi-driver conflict). DP16KD=0 on both is expected: M3's
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BRAM-backed buffers (activation/weight/result_buffer) are
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deliberately NOT instantiated inside dataflow_core yet (decisions.log
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DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
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every prior per-processor DSP measurement since M1/M2).
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[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
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standalone top-level synthesis -- no timing harness needed: real PSRAM
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pins replace dataflow_core's wide per-slot arrays, total 157 port bits,
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well under the LFE5U-45F-8BG381's ~245 TRELLIS_IO budget)
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LUT4=3145 CCU2C=388 TRELLIS_FF=3659 MULT18X18D=16 DP16KD=0
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TRELLIS_DPR16X4=45 (small LUT-based distributed RAM, inferred from
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neural_director's shallow QUEUE_DEPTH-entry job queue -- not BRAM,
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same primitive class already seen in M7's own harness stat)
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$_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
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from V1's own unmodified psram_controller.v)
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CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
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...neural_processor.\gi" warnings documented since EXP-0001).
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