micheleandClaude Sonnet 5
6cff2c8a7c
neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around the real, unmodified V1 PSRAM backend chain (int8_memory_access -> memory_interface -> psram_controller), funneling N_SLOTS independent Memory Backend Interface ports through a new generic N-port arbiter (slot_mem_arbiter.v) inspired by (not copied from) V1's own mem_arbiter.v. Real concurrent-slot simulation immediately surfaced a genuine bug (ERR-0008): memory_manager/prefetch_engine's byte-level backend protocol is fire-and-forget (a single-cycle mem_req pulse with no accept handshake) - correct for M4's direct 1:1 connection, but a naive arbiter silently drops a pulse arriving while the shared bus is owned by another slot, hanging that slot forever. Fixed with a per-port pending-request latch, the same "queue, don't drop" idiom already used by memory_manager's own pf_pending register (ERR-0006). Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for one real PSRAM port (444 cycles). No regression on M4's own testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45 MHz, PASS at 80MHz. Arbitration policy is fixed lowest-index priority, not fairness- balanced (DEC-0010) - consistent with every other "simplest correct policy first" scheduling choice in this roadmap, revisited only if M9's real measurement shows starvation matters. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/ experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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FPGA-Neural V2 — stato roadmap
Fonte del mandato: docs/v2-description.md (root del repository). Baseline
funzionale/numerica/bit-exact: hardware/v1/ (frozen, sola lettura — vedi
hardware/v1/README.md).
Legenda: [ ] non iniziato · [~] in corso · [x] completo (sim+synth+timing
reali, non solo scritto).
- M1 — Neural Processor (
hardware/v2/rtl/neural_processor.v, P8). Bit-exact vs V1 (7/7 test, Verilator), pipeline a 8 stadi funzionante, throughput reale (1 tile/ciclo). Sintesi reale: 0 problemi CHECK, Fmax 183.12 MHz (ACC_WIDTH=32) — vedilogs/experiments.logEXP-0001/EXP-0002,logs/errors.logper 3 bug reali trovati e risolti (2 del toolchain Icarus, 1 RTL). - M2 — Processor Array (
neural_processor_array.v). 1/2/4/8 processor testati (sim concorrenza reale + sintesi/P&R reali). Fmax sempre PASS a 80MHz (159.11→134.70 MHz). Scoperta: il DSP (MULT18X18D), non LUT/FF, satura per primo (88% a N=8) — vedilogs/decisions.logDEC-0005. - M3 — Buffers (
activation_buffer.v,weight_buffer.v,result_buffer.v). Tutti inferiscono DP16KD reale (10/10 test, 6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di weight_buffer e' guidato da P_IN (larghezza), non da DEPTH. - M4 — Memory Manager (
memory_manager.v,prefetch_engine.v), backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3 job PASS) con vero neural_processor + vera catena PSRAM V1. 3 bug RTL trovati/risolti (logs/errors.logERR-0006). Fmax 165.86 MHz. - M5 — Neural Director (
neural_director.v), scheduling first-free. 4/4 test PASS (dispatch + coda + backpressure reale su N_SLOTS=2). FSM ridotta a 4 stati, dependency rimandata a M6 (logs/decisions.logDEC-0007). Fmax 250.50 MHz. - M6 — Dependency Manager (
dependency_manager.v), ready/waiting queue, dependency counters, wake-up, producer tracking. 4/4 test PASS (dipendenze multiple + produttore condiviso/piu' consumer). Fmax 155.30 MHz. Forwarding di valori e riuso slot rimandati (logs/decisions.logDEC-0008). - M7 — Dataflow Core (
dataflow_core.v), prima integrazione completa: Dependency Manager (M6) -> Neural Director (M5) -> N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)), loop di wake-up chiuso end-to-end. 4/4 test PASS su un DAG a 3 nodi (node2 dipende da entrambi node0+node1, dispatch confermato solo dopo che ENTRAMBI completano davvero). Sintesi reale 0 problemi a N_SLOTS=2 e N_SLOTS=4. Fmax reale (harness): 165.15 MHz (N_SLOTS=2), 133.19 MHz (N_SLOTS=4). Buffer M3 e arbitraggio PSRAM condiviso rimandati esplicitamente a M8 (logs/decisions.logDEC-0009). - M8 — PSRAM integration (
neural_multiprocessor.v,slot_mem_arbiter.v), controller V1 riusato SENZA MODIFICHE, condiviso tra N_SLOTS memory_manager concorrenti reali. Trovato e risolto un bug RTL reale: il primo arbitro perdeva silenziosamente una richiesta arrivata durante la contesa (protocollo byte-level "fire-and-forget", mai esposto da M4 che collega un solo master direttamente) — vedilogs/errors.logERR-0008. Dopo il fix: 4/4 test PASS (2 slot in vera contesa concorrente sulla stessa PSRAM reale). Sintesi reale 0 problemi (nessun harness necessario — pin reali PSRAM tengono il top-level a 157 pin). Fmax reale 142.45 MHz. Politica di arbitraggio a priorità fissa, non ancora fair (logs/decisions.logDEC-0010). - M9 — Full benchmark, tabella V1 vs V2 (§32 del mandato).
- M10 — Optimization, solo sulla base dei dati raccolti in M1-M9.
Log
Vedi hardware/v2/logs/ (development.log per la cronologia di sessione,
decisions.log per le decisioni architetturali con motivazione,
experiments.log per ogni EXP-XXXX end-to-end).
Regole non negoziabili attive (§34 del mandato, per riferimento rapido)
- V1 (
hardware/v1/) rimane intatta — mai modificata. - V2 vive esclusivamente sotto
hardware/v2/. - Nessun risultato inventato: THEORETICAL vs SIMULATED vs SYNTHESIZED vs POST-P&R sempre etichettati esplicitamente.
- Ogni modifica/esperimento/decisione registrata nei log, mai persa.
- Ogni esperimento ha un ID univoco, mai riutilizzato — anche i FAIL restano.