micheleandClaude Sonnet 5
ccaf3ee059
Adds result_writeback.v, one instance per packed_slot.v, writing each completed job's result directly into DDR3 at the job's own result_addr_a/b instead of driving literal top-level pins -- the same architectural shape as the weight-fetch path, in reverse. job_done now means "durably in DDR3", not "captured in a register only a pin could see". n2_system_ddr3_top.v's own s0_result_data_a/b, s1_result_data_a/b top-level package pins are removed (and the now-dangling XDC constraint for them), closing the real, hard scaling blocker docs/ARCHITECTURE_ ANALYSIS.md flagged since EXP-0074/0079 (8 bits x 2 lanes x N cores -> 256 pins at N=16). Addressing reuses the exact same JOB_ADDR_WIDTH->ctrl-bus-word truncation x_base_a/w_base already use (verified against act_tile_ fetch.v's/layer_prefetch_ctrl.v's own real code, not guessed). The host reads results back via the already-existing READ_MEM (0x02) SPI opcode -- no new protocol. A real EXP-0066-class bug (issuing ctrl_req before mem_grant) was caught and fixed before ever compiling, by re-deriving the design against act_tile_fetch.v's own proven S_MEMWAIT/S_GAP sequencing. Verified two ways: tb_packed_slot.v extended with a real DDR3 read-after-write check (9/9 PASS, confirms the write actually landed, not just that job_done pulsed); tb_n2_system_ddr3.v re-run via real xsim to confirm correct behavior under real 2-slot shared-bus arbitration (8/8 PASS, 0 errors, consistent timing with EXP-0087's own baseline for this workload). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
193 lines
8.6 KiB
Verilog
193 lines
8.6 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// V3 -- result_writeback.v: real result-writeback engine, closing the
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// gap disclosed since packed_slot.v's own original header ("no
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// result-writeback engine exists yet either -- result_addr_a/b are
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// passed through unused") and flagged as a hard scaling blocker
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// (docs/ARCHITECTURE_ANALYSIS.md S4.6/S5.3): literal top-level
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// result_data_a/b pins do not scale past a handful of cores (8 bits x
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// 2 lanes x N cores -- at N=16 that's 256 pins on this port alone).
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//
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// REAL FIX: write each completed job's result INTO DDR3 at the job's
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// own result_addr_a/result_addr_b (already carried through packed_
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// slot.v's own interface, previously unused), reusing the SAME shared
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// ctrl port packed_slot.v already time-multiplexes among its other
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// sub-engines (layer_prefetch_ctrl.v / ddr_prefetch_mgr.v) -- same
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// architectural shape as the weight-fetch path, in reverse. The host
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// reads results back via the ALREADY-EXISTING READ_MEM (0x02) opcode
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// -- no new SPI protocol needed.
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//
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// REAL ADDRESSING (verified against act_tile_fetch.v's/layer_
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// prefetch_ctrl.v's own real address-computation code, not guessed):
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// result_addr_a/b arrive in packed_slot.v's own JOB_ADDR_WIDTH=26-bit
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// convention. Exactly like x_base_a/w_base already do, the LOW
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// ADDR_WIDTH=25 bits (dropping the unused top/MSB headroom bit) are
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// used DIRECTLY as a ctrl-bus-native 32-bit-word address -- the SAME
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// address space act_tile_fetch.v's own ctrl_addr already lives in.
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// ONE full 32-bit ctrl-word is written per lane:
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// {node_id[15:0], 8'h00, result_data[7:0]} (low 16 bits =
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// zero-extended 8-bit result value, high 16 bits = node_id).
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//
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// REAL, DISCLOSED HOST-FIRMWARE IMPLICATION (not yet built, same as
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// this project's other disclosed host-firmware gaps, e.g. JTAG
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// bit-banging): reading a written result back via the EXISTING
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// READ_MEM (16-bit-word-addressed) opcode needs
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// `mem_addr = result_addr[24:0]*2` for the value and
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// `mem_addr = result_addr[24:0]*2 + 1` for node_id (2 host reads per
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// lane, since READ_MEM's own mem_addr is 16-bit-word-granular while
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// this engine writes a native 32-bit ctrl-word -- see host_mem_
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// bridge.v's own header for the real reason that halving exists).
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//
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// WMASK CONVENTION (matches host_mem_bridge.v's own real, already-
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// working pattern exactly, not reinvented): 0 = write this byte, 1 =
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// masked -- the same DQM-style polarity this project's whole memory
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// stack already uses end to end.
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//
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// TWO LANES, ONE TRANSACTION EACH, SEQUENTIAL: lane A's write
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// completes fully (through its own ctrl_ready) before lane B's own
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// starts -- mirrors act_tile_fetch.v's own "lane A then lane B"
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// sequencing for its two burst reads, the same discipline already
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// proven safe on this shared bus.
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// ============================================================
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module result_writeback #(
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parameter BURST_LEN = 8,
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parameter DATA_WIDTH = 8,
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parameter JOB_ADDR_WIDTH = 26,
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parameter ADDR_WIDTH = 25 // ctrl-bus-native word address, matches sdram_arbiter_n.v's own convention
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)(
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input wire clk,
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input wire rst,
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// one-shot request: pulse `start` with all fields valid the same
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// cycle (matches this project's own established one-shot-pulse-
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// requester discipline, EXP-0066).
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input wire start,
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input wire [JOB_ADDR_WIDTH-1:0] result_addr_a,
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input wire [JOB_ADDR_WIDTH-1:0] result_addr_b,
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input wire signed [DATA_WIDTH-1:0] result_data_a,
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input wire signed [DATA_WIDTH-1:0] result_data_b,
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input wire [15:0] result_node_id_a,
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input wire [15:0] result_node_id_b,
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output wire busy,
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output reg done, // one-cycle pulse
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// ---- shared ctrl port (packed_slot.v's own local mux gates this
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// the same way it already gates pf_ctrl_*/act_ctrl_*) ----
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output wire mem_active,
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input wire mem_grant,
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output reg ctrl_req,
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output reg ctrl_wr,
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output reg [ADDR_WIDTH-1:0] ctrl_addr,
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output reg [32*BURST_LEN-1:0] ctrl_wdata,
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output reg [4*BURST_LEN-1:0] ctrl_wmask,
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input wire [32*BURST_LEN-1:0] ctrl_rdata,
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input wire ctrl_ready,
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input wire ctrl_busy
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);
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localparam ALIGN_BITS = $clog2(BURST_LEN); // 3: which of the BURST_LEN 32-bit words in the burst
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localparam S_IDLE = 3'd0,
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S_MEMWAIT = 3'd1,
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S_XFER_A = 3'd2,
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S_GAP = 3'd3, // wait for ctrl_busy to clear before firing lane B's request
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S_XFER_B = 3'd4,
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S_DONE = 3'd5;
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reg [2:0] state;
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reg [DATA_WIDTH-1:0] data_a_lat, data_b_lat;
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reg [15:0] nid_a_lat, nid_b_lat;
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reg [ADDR_WIDTH-1:0] word_addr_a_lat, word_addr_b_lat;
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assign busy = (state != S_IDLE);
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// real, established discipline (EXP-0066): mem_active must be
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// visible to the arbiter the SAME cycle this module first wants
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// the bus, i.e. as soon as it leaves S_IDLE -- not only once a
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// transaction is actually in flight.
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assign mem_active = (state != S_IDLE);
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// real ctrl-bus-native word address: low ADDR_WIDTH bits of the
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// JOB_ADDR_WIDTH job address -- the exact same truncation act_
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// tile_fetch.v/layer_prefetch_ctrl.v already apply to x_base_a/
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// w_base (verified against their own real code, not guessed).
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wire [ADDR_WIDTH-1:0] word_addr_a = result_addr_a[ADDR_WIDTH-1:0];
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wire [ADDR_WIDTH-1:0] word_addr_b = result_addr_b[ADDR_WIDTH-1:0];
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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ctrl_req <= 1'b0;
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ctrl_wr <= 1'b0;
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done <= 1'b0;
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end else begin
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ctrl_req <= 1'b0;
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done <= 1'b0;
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case (state)
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S_IDLE: begin
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if (start) begin
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data_a_lat <= result_data_a;
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data_b_lat <= result_data_b;
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nid_a_lat <= result_node_id_a;
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nid_b_lat <= result_node_id_b;
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word_addr_a_lat <= word_addr_a;
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word_addr_b_lat <= word_addr_b;
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state <= S_MEMWAIT;
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end
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end
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// real, established discipline (EXP-0066): never issue
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// ctrl_req before mem_grant is actually observed -- a
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// blind/early ctrl_req on a shared, arbitrated bus can
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// lose the request permanently.
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S_MEMWAIT: begin
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if (mem_grant) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b1;
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ctrl_addr <= {word_addr_a_lat[ADDR_WIDTH-1:ALIGN_BITS], {ALIGN_BITS{1'b0}}};
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ctrl_wdata <= {(BURST_LEN){nid_a_lat, 8'h00, data_a_lat}};
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ctrl_wmask <= ~({{(4*BURST_LEN-4){1'b0}}, 4'hF} << (word_addr_a_lat[ALIGN_BITS-1:0] * 4));
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state <= S_XFER_A;
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end
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end
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S_XFER_A: begin
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if (ctrl_ready) begin
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state <= S_GAP;
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end
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end
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// mig_native_adapter.v's own S_DONE state keeps `busy`
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// asserted one cycle past ctrl_ready (act_tile_fetch.v's
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// own header/code already established this) -- wait for
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// !ctrl_busy before firing lane B's write, instead of
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// assuming back-to-back is safe.
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S_GAP: begin
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if (!ctrl_busy) begin
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ctrl_req <= 1'b1;
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ctrl_wr <= 1'b1;
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ctrl_addr <= {word_addr_b_lat[ADDR_WIDTH-1:ALIGN_BITS], {ALIGN_BITS{1'b0}}};
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ctrl_wdata <= {(BURST_LEN){nid_b_lat, 8'h00, data_b_lat}};
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ctrl_wmask <= ~({{(4*BURST_LEN-4){1'b0}}, 4'hF} << (word_addr_b_lat[ALIGN_BITS-1:0] * 4));
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state <= S_XFER_B;
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end
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end
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S_XFER_B: begin
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if (ctrl_ready) begin
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state <= S_DONE;
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end
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end
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S_DONE: begin
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done <= 1'b1;
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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