FPGA-Neural

T

micheleandClaude Sonnet 5 67ccb420d6 docs: real P&R directive tuning closes most of remaining N=16 timing gap (EXP-0094 cont.)

Same RTL, real Vivado strategy directives (Explore/ExtraNetDelay_high/
AggressiveExplore, zero RTL risk): WNS -0.646ns -> -0.338ns, TNS
-97.5ns -> -5.3ns, failing endpoints 771 -> 60. Remaining bottleneck
confirmed intrinsic (84% logic delay, DSP48E1->CARRY4 path inside
neural_processor_packed.v, recurring per-PE) -- unlikely to shrink
further via P&R strategy alone.

Cumulative: two safe fixes (hierarchical arbiter + directive tuning)
close ~89% of the original TNS gap and ~63% of WNS, neither touching
neural_processor_packed.v. Deliberate stop: closing the rest needs
that shared, load-bearing module touched -- a larger, more careful
step (verify against both N=2 and N=16) documented as next_action,
not attempted without further direction.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-21 02:39:45 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: real P&R directive tuning closes most of remaining N=16 timing gap (EXP-0094 cont.)

2026-09-21 02:39:45 +02:00

hardware

docs: real P&R directive tuning closes most of remaining N=16 timing gap (EXP-0094 cont.)

2026-09-21 02:39:45 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze