micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1.5 KiB
1.5 KiB
| 1 | metric | n_slots2 | n_slots4 | unit | classification |
|---|---|---|---|---|---|
| 2 | sdram_req_count | 4096 | 4096 | transactions | INTEGRATED BENCHMARK |
| 3 | sdram_ready_count | 4096 | 4096 | transactions | INTEGRATED BENCHMARK |
| 4 | sdram_wr_count | 0 | 0 | transactions (weight fetch is read-only) | INTEGRATED BENCHMARK |
| 5 | sdram_busy_cycles | 49404 | 49392 | cycles | INTEGRATED BENCHMARK |
| 6 | sdram_busy_pct | 94.71 | 99.92 | percent of total_cycles | DERIVED |
| 7 | sdram_refresh_count | 42 | 40 | real AUTO REFRESH commands issued | INTEGRATED BENCHMARK |
| 8 | sdram_request_latency_min | 10 | 10 | cycles (req-to-ready single controller port) | INTEGRATED BENCHMARK |
| 9 | sdram_request_latency_max | 16 | 16 | cycles | INTEGRATED BENCHMARK |
| 10 | sdram_request_latency_avg | 10.06 | 10.06 | cycles | INTEGRATED BENCHMARK |
| 11 | isolated_single_txn_cycles_80mhz | 10 | 10 | cycles (Phase 4/6 isolated regression baseline) | RTL SIMULATION |
| 12 | n_way_arbitration_overhead_cycles_per_tile | 2.73 | 2.07 | cycles/tile (measured cycles/tile minus isolated single-txn cost) | DERIVED |
| 13 | sdram_avg_bytes_per_cycle | 0.6282 | 0.6629 | bytes/cycle | DERIVED |
| 14 | sdram_sustained_bandwidth_mb_s | 50.26 | 53.04 | MB/s (bytes_per_cycle * 80MHz) | DERIVED |
| 15 | sdram_nominal_bandwidth_mb_s | 160.0 | 160.0 | MB/s (2 bytes x16 * 80MHz) | THEORETICAL |
| 16 | bandwidth_utilization_pct | 31.4 | 33.2 | percent of nominal | DERIVED |
| 17 | bottleneck_classification | MEMORY_BANDWIDTH_LIMIT | MEMORY_BANDWIDTH_LIMIT | qualitative (sdram_busy_pct near-saturated, avg latency near the fixed minimum -> not latency-bound; modest N-way arbitration overhead present but small relative to the controller's own fixed per-transaction cost -> not primarily arbitration-bound) | DERIVED |