FPGA-Neural

T

michele 678caa9bce docs: real timing closure for 32-bit DDR3 channel (EXP-0086)

Reverting Clock Period to 3225ps (keeping Data Width=32) closes real
timing: WNS=+0.095707ns, WHS=+0.036275ns, 0 failing endpoints, all
user-specified constraints met. This is the real final signoff for the
32-bit DDR3 channel widening effort (EXP-0083 through EXP-0086),
replacing EXP-0083's 16-bit-era baseline as the project's current
trustworthy number. Confirms the EXP-0084 root-cause analysis: the
earlier -0.618ns failure was caused by a separate, stacked clock
speedup, not the width change itself.

Also found and fixed a second, wholesale real occurrence of the
stale-import bug: the MIG wizard regeneration needed to revert Clock
Period silently re-imported the entire v3 RTL tree (9 files) plus the
top XDC back to pre-EXP-0084 stale copies, not just the file(s) the
regeneration touched. CLAUDE.md's lesson extended accordingly.

2026-09-20 18:05:30 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: real timing closure for 32-bit DDR3 channel (EXP-0086)

2026-09-20 18:05:30 +02:00

hardware

docs: real timing closure for 32-bit DDR3 channel (EXP-0086)

2026-09-20 18:05:30 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze