micheleandClaude Sonnet 5
7e2711fa27
Bumps ADDR_WIDTH's default from 22 to 23 bits across every RTL module (neuron_memory, layer_sequencer, spi_engine, spi_neuron_top, mem_arbiter, int8_memory_access, memory_interface, psram_controller, memory_model) and every testbench that mirrors it, so the system's byte-address space reaches the full 8 MiB the recommended PSRAM part (ISSI IS66WVE4M16EBLL-70BLI, docs/FPGA-Neural-Hardware-Design.md §3) actually provides -- previously only 4 MiB (half the chip) was reachable, since int8_memory_access.v's byte->word address shift (addr >> 1) turned the old 22-bit byte address into only 21 real word bits, one short of the chip's real 22-bit word address (A0-A21). At 23 bits, that same shift lands exactly on all 22 chip address lines, so the whole part is usable now instead of deferred to a future widening. Also fixes a stray 22'd11-sized literal in layer_sequencer.v's descriptor-table address increment (numerically already safe via Verilog's zero-extension, but now correctly unsized so it always matches ADDR_WIDTH instead of silently assuming 22). Updated docs/FPGA-NeuralNetwork-Engine.md's SPI protocol address-field note (23 bits, top 1 reserved bit instead of 2) and docs/FPGA-Neural-Hardware-Design.md's PSRAM section (the "chip has one spare address line" framing is gone now that all 22 are wired and used). Full regression (all 11 ADDR_WIDTH-touching testbenches, plus a Yosys elaboration check of spi_neuron_top with the new default and no override) passes clean. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
409 lines
13 KiB
Verilog
409 lines
13 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// SPI_NEURON_TOP END-TO-END TESTBENCH
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//
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// Drives the FULL real stack (spi_slave + spi_engine + mem_arbiter
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// + int8_memory_access + memory_interface + psram_controller +
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// psram_model) purely over simulated SPI -- no direct injection
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// into neuron_memory's ports. This is the "verified with the real
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// RAM" test: everything WRITE_RAM/READ_RAM/neuron_memory touches
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// goes through the actual PSRAM timing model, not a synthetic mock.
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//
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// Session (matches docs §8.1 example + neuron_memory_tb.v scenarios,
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// this time reached only through the SPI opcode set):
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// RESET -> READ_CONFIG -> WRITE_RAM(X) -> WRITE_RAM(W) ->
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// WRITE_RAM(bias) -> READ_RAM verify -> SET_BASE x3 -> START ->
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// poll STATUS -> READ_OUTPUT
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//
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// TEST 1: X=1 (32x), W=1, bias=0 -> y = 32
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// TEST 2: reload W=4 -> y saturates to 127
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// TEST 3: reload W=-1 -> ReLU -> y = 0
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// ================================================================
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module tb;
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localparam ADDR_WIDTH = 23;
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localparam DATA_WIDTH = 8;
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localparam N_INPUTS = 32;
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localparam N_NEURONS = 1;
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localparam PARALLEL = 8;
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localparam ACC_WIDTH = 32;
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localparam MEM_DATA_WIDTH = 16;
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localparam CLK_PERIOD = 12.5; // 80 MHz
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reg clk;
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reg rst;
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initial begin
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clk = 1'b0;
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forever #(CLK_PERIOD / 2.0) clk = ~clk;
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end
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reg sclk;
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reg mosi;
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wire miso;
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reg cs_n;
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wire [ADDR_WIDTH-1:0] psram_a;
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wire [MEM_DATA_WIDTH-1:0] psram_dq;
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wire psram_ce_n, psram_oe_n, psram_we_n, psram_lb_n, psram_ub_n, psram_zz_n;
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spi_neuron_top #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH),
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.MEM_DATA_WIDTH(MEM_DATA_WIDTH),
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.CLK_FREQ_MHZ(80)
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) dut (
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.clk(clk), .rst(rst),
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.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
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.psram_a(psram_a), .psram_dq(psram_dq),
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.psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n),
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.psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n)
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);
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psram_model #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(MEM_DATA_WIDTH),
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.DEPTH(16384)
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) u_psram (
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.clk(clk),
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.a(psram_a), .dq(psram_dq),
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.ce_n(psram_ce_n), .oe_n(psram_oe_n), .we_n(psram_we_n),
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.lb_n(psram_lb_n), .ub_n(psram_ub_n), .zz_n(psram_zz_n)
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);
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// ============================================================
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// SPI MASTER BFM
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// ============================================================
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task clk_wait;
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input integer n;
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integer k;
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begin
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for (k = 0; k < n; k = k + 1)
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@(posedge clk);
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end
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endtask
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task spi_begin;
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input integer half_bit_cycles;
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begin
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cs_n = 1'b1;
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sclk = 1'b0;
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mosi = 1'b0;
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clk_wait(half_bit_cycles * 2);
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cs_n = 1'b0;
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clk_wait(half_bit_cycles * 2);
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end
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endtask
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task spi_end;
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input integer half_bit_cycles;
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begin
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clk_wait(half_bit_cycles * 2);
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cs_n = 1'b1;
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clk_wait(half_bit_cycles * 2);
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end
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endtask
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task spi_xfer_byte;
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input [7:0] tx;
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input integer half_bit_cycles;
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output [7:0] rx;
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integer i;
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reg [7:0] rx_acc;
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begin
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rx_acc = 8'h00;
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for (i = 7; i >= 0; i = i - 1) begin
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mosi = tx[i];
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clk_wait(half_bit_cycles);
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sclk = 1'b1;
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rx_acc[i] = miso;
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clk_wait(half_bit_cycles);
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sclk = 1'b0;
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clk_wait(half_bit_cycles);
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end
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rx = rx_acc;
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end
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endtask
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// RAM-touching bytes need enough margin for the real PSRAM
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// chain's latency (psram_controller ACCESS_CYCLES ~= ceil(70ns
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// * 80MHz) = 6 cycles, plus memory_interface/int8_memory_access/
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// arbiter overhead -- comfortably covered by 40 cycles/half-bit).
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localparam HB_RAM = 40;
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// Pure register opcodes (SET_BASE/START/STATUS/READ_OUTPUT/
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// READ_CONFIG/RESET) only need CDC margin (~4 cycles).
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localparam HB_REG = 8;
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reg [7:0] rx_tmp;
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integer errors;
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integer i;
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integer poll_count;
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// ============================================================
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// HELPER TASKS
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// ============================================================
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task do_reset;
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begin
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spi_begin(HB_REG);
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spi_xfer_byte(8'h0F, HB_REG, rx_tmp); // RESET
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spi_end(HB_REG);
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end
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endtask
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task set_base;
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input [7:0] sel;
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input [ADDR_WIDTH-1:0] addr;
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begin
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spi_begin(HB_REG);
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spi_xfer_byte(8'h10, HB_REG, rx_tmp);
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spi_xfer_byte(sel, HB_REG, rx_tmp);
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spi_xfer_byte(addr[23:16], HB_REG, rx_tmp);
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spi_xfer_byte(addr[15:8], HB_REG, rx_tmp);
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spi_xfer_byte(addr[7:0], HB_REG, rx_tmp);
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spi_end(HB_REG);
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end
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endtask
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task write_ram_const;
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input [ADDR_WIDTH-1:0] addr;
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input integer len;
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input signed [7:0] value;
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integer k;
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begin
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spi_begin(HB_RAM);
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spi_xfer_byte(8'h01, HB_RAM, rx_tmp);
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spi_xfer_byte(addr[23:16], HB_RAM, rx_tmp);
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spi_xfer_byte(addr[15:8], HB_RAM, rx_tmp);
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spi_xfer_byte(addr[7:0], HB_RAM, rx_tmp);
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spi_xfer_byte(len[15:8], HB_RAM, rx_tmp);
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spi_xfer_byte(len[7:0], HB_RAM, rx_tmp);
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for (k = 0; k < len; k = k + 1)
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spi_xfer_byte(value, HB_RAM, rx_tmp);
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spi_end(HB_RAM);
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end
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endtask
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task read_ram_byte;
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input [ADDR_WIDTH-1:0] addr;
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output [7:0] data;
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begin
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spi_begin(HB_RAM);
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spi_xfer_byte(8'h02, HB_RAM, rx_tmp);
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spi_xfer_byte(addr[23:16], HB_RAM, rx_tmp);
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spi_xfer_byte(addr[15:8], HB_RAM, rx_tmp);
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spi_xfer_byte(addr[7:0], HB_RAM, rx_tmp);
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spi_xfer_byte(8'h00, HB_RAM, rx_tmp);
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spi_xfer_byte(8'h01, HB_RAM, rx_tmp);
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spi_xfer_byte(8'h00, HB_RAM, data);
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spi_end(HB_RAM);
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end
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endtask
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task read_status;
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output [7:0] status;
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begin
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spi_begin(HB_REG);
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spi_xfer_byte(8'h21, HB_REG, rx_tmp);
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spi_xfer_byte(8'h00, HB_REG, status);
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spi_end(HB_REG);
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end
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endtask
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task do_start;
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begin
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spi_begin(HB_REG);
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spi_xfer_byte(8'h20, HB_REG, rx_tmp);
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spi_end(HB_REG);
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end
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endtask
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task wait_done;
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reg [7:0] status;
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begin
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poll_count = 0;
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status = 8'h00;
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while (!status[1] && poll_count < 1000) begin
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clk_wait(20);
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read_status(status);
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poll_count = poll_count + 1;
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end
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if (!status[1]) begin
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$display(" FAIL: done never asserted (poll_count=%0d)", poll_count);
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errors = errors + 1;
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end
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end
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endtask
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task read_output_byte0;
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output signed [7:0] y0;
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begin
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spi_begin(HB_REG);
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spi_xfer_byte(8'h22, HB_REG, rx_tmp);
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spi_xfer_byte(8'h00, HB_REG, y0);
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spi_end(HB_REG);
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end
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endtask
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// ============================================================
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// MAIN
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// ============================================================
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reg signed [7:0] y_result;
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reg [7:0] cfg_byte;
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reg [7:0] verify_byte;
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initial begin
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$dumpfile("sim/spi_neuron_top.vcd");
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$dumpvars(0, tb);
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rst = 1'b1;
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cs_n = 1'b1;
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sclk = 1'b0;
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mosi = 1'b0;
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errors = 0;
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repeat (5) @(posedge clk);
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rst = 1'b0;
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// Wait for PSRAM controller initialization (same as
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// sim/neuron_memory_tb.v).
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wait (dut.u_psram_ctrl.state == dut.u_psram_ctrl.STATE_IDLE);
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$display("");
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$display("========================================");
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$display("SPI_NEURON_TOP END-TO-END TEST (real PSRAM)");
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$display("========================================");
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// --------------------------------------------------------
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// RESET (opcode) + READ_CONFIG
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// --------------------------------------------------------
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do_reset;
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spi_begin(HB_REG);
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spi_xfer_byte(8'h30, HB_REG, rx_tmp);
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== ADDR_WIDTH[7:0]) begin $display(" FAIL: READ_CONFIG ADDR_WIDTH"); errors = errors + 1; end
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== N_INPUTS[15:8]) begin $display(" FAIL: READ_CONFIG N_INPUTS hi"); errors = errors + 1; end
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== N_INPUTS[7:0]) begin $display(" FAIL: READ_CONFIG N_INPUTS lo"); errors = errors + 1; end
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== N_NEURONS[7:0]) begin $display(" FAIL: READ_CONFIG N_NEURONS"); errors = errors + 1; end
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== PARALLEL[7:0]) begin $display(" FAIL: READ_CONFIG PARALLEL"); errors = errors + 1; end
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spi_xfer_byte(8'h00, HB_REG, cfg_byte);
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if (cfg_byte !== DATA_WIDTH[7:0]) begin $display(" FAIL: READ_CONFIG DATA_WIDTH"); errors = errors + 1; end
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spi_end(HB_REG);
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$display("READ_CONFIG: %0s", (errors == 0) ? "PASS" : "FAIL");
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// --------------------------------------------------------
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// Load X=1 (32x), W=1 (32x), bias=0 into real PSRAM over SPI
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// --------------------------------------------------------
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write_ram_const(22'h000000, N_INPUTS, 8'sd1); // X
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write_ram_const(22'h000100, N_INPUTS, 8'sd1); // W
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write_ram_const(22'h000200, 1, 8'sd0); // bias
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// Verify one written byte reads back correctly through the
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// real PSRAM (READ_RAM), confirming the write actually
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// landed and isn't just accepted-but-dropped.
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read_ram_byte(22'h000000, verify_byte);
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if (verify_byte !== 8'sd1) begin
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$display(" FAIL: READ_RAM verify X[0] = 0x%02x expected 0x01", verify_byte);
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errors = errors + 1;
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end else begin
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$display("READ_RAM verify: PASS (X[0]=0x%02x)", verify_byte);
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end
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set_base(8'h00, 22'h000000); // X_BASE
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set_base(8'h01, 22'h000100); // W_BASE
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set_base(8'h02, 22'h000200); // BIAS_ADDR
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// --------------------------------------------------------
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// TEST 1: 32 * 1 * 1 + 0 = 32
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// --------------------------------------------------------
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do_start;
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wait_done;
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read_output_byte0(y_result);
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$display("");
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$display("TEST 1 (SUM=32): y = %0d (expected 32)", y_result);
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if (y_result !== 8'sd32) begin
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$display(" FAIL");
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errors = errors + 1;
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end else begin
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$display(" PASS");
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end
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// --------------------------------------------------------
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// TEST 2: reload W=4 -> 32*1*4 = 128 -> saturate to 127
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// --------------------------------------------------------
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write_ram_const(22'h000100, N_INPUTS, 8'sd4);
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do_start;
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wait_done;
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read_output_byte0(y_result);
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$display("");
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$display("TEST 2 (SATURATION): y = %0d (expected 127)", y_result);
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if (y_result !== 8'sd127) begin
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$display(" FAIL");
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errors = errors + 1;
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end else begin
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$display(" PASS");
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end
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// --------------------------------------------------------
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// TEST 3: reload W=-1 -> 32*1*(-1) = -32 -> ReLU -> 0
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// --------------------------------------------------------
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write_ram_const(22'h000100, N_INPUTS, -8'sd1);
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do_start;
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wait_done;
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read_output_byte0(y_result);
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$display("");
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$display("TEST 3 (RELU): y = %0d (expected 0)", y_result);
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if (y_result !== 8'sd0) begin
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$display(" FAIL");
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errors = errors + 1;
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end else begin
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$display(" PASS");
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end
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// --------------------------------------------------------
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// SUMMARY
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// --------------------------------------------------------
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$display("");
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$display("========================================");
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if (errors == 0)
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$display("SPI_NEURON_TOP END-TO-END TEST PASSED");
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else
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$display("SPI_NEURON_TOP END-TO-END TEST FAILED: %0d errors", errors);
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$display("========================================");
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$display("");
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$finish;
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end
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endmodule
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