micheleandClaude Sonnet 5
43abf28b5b
STEP20 work toward the V2 hardware release gate. Adds real new RTL
implementing the three pieces the previous freeze (V2.0.0) explicitly
left open, plus real, disclosed verification findings. Does NOT
declare hardware release complete -- see below.
New RTL:
- spi_host_bridge.v: real SPI slave protocol engine (WRITE_JOB/
WRITE_MEM/READ_MEM/STATUS/RESET opcodes), replacing the 110-pin
reg_* testbench bus as the intended physical host interface.
Isolated regression 18/18 PASS (tb_spi_host_bridge.v); two real
MISO-timing bugs found and fixed during its own development (see
the module's header for the root-cause writeup).
- ecp5_pll_sys_clk.v: real, tool-generated (Project Trellis ecppll)
EHXPLLL wrapper, 16MHz oscillator -> 64MHz system clock, with a
declared (not fabricated) simulation-only PLL bypass.
- reset_sync.v: standard async-assert/sync-deassert reset bridge
gating on external POR and PLL lock.
- fpga_neural_v2_top.v: board-level top wiring the above around the
STEP19 compute+memory design's own already-frozen submodules
(zero modification to neural_processor.v, dependency_manager.v,
sdram_unified_backend.v, or any other previously-frozen file).
Real findings from this step's own re-verification (both logged in
full in hardware/v2/logs/errors.log):
- ERR-0024: the current Icarus Verilog v13.0 install (updated since
the last freeze) gives WRONG bit-exact results for the
already-committed STEP19 regression. Cross-checked against
Verilator per this project's own standing protocol (DEC-0004) --
the STEP19 baseline (single SDRAM, N=2/N=4, raw reg_* interface) IS
bit-exact correct, reconfirmed today, matching the historical cycle
counts exactly. Two provably-zero-behavior-change declaration-order
fixes were required just to get the current toolchain to elaborate
the already-shipped STEP19 files at all.
- ERR-0025: a real SPI-bridge protocol race (fixed) plus a SEPARATE,
real, UNRESOLVED defect -- two jobs dispatched through the real SPI
path with realistic pacing produce wrong compute results, even
though job registration itself is confirmed correct at the
handshake. Root cause not yet isolated. Committed as a known-failing
regression (tb_fpga_neural_v2_top_smoke.v) documenting the gap
honestly rather than hiding it.
Given ERR-0025 Part B is real and unresolved, synthesis/P&R of the new
board-level top was deliberately not attempted this round, and V2
hardware release is NOT declared complete. See decisions.log DEC-0036
and hardware/v2/docs/{CHIP_READINESS,OPEN_ITEMS}.md for the full,
itemized status.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
35 lines
1.2 KiB
Verilog
35 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
|
|
|
|
// ================================================================
|
|
// FPGA-Neural V2 -- reset synchronizer (STEP20, real reset/POR path)
|
|
//
|
|
// Standard async-assert / sync-deassert double-flop reset bridge.
|
|
// Asserts `rst` IMMEDIATELY (combinationally) when either the
|
|
// external POR/supervisor (ext_rst_n, active-low) is asserted OR the
|
|
// PLL has not yet reported LOCK -- both real, physical conditions
|
|
// under which no downstream logic (SDRAM controller, dependency
|
|
// manager, SPI bridge) may be considered valid. Deassertion is
|
|
// synchronized to `clk_sys` through two flip-flops so no downstream
|
|
// flop ever sees an asynchronous release edge.
|
|
// ================================================================
|
|
|
|
module reset_sync (
|
|
input wire clk_sys,
|
|
input wire ext_rst_n, // external POR/supervisor, active-low
|
|
input wire pll_locked,
|
|
output wire rst // synchronous-deassert, active-high
|
|
);
|
|
|
|
wire async_rst_n = ext_rst_n & pll_locked;
|
|
|
|
reg [1:0] sync_ff;
|
|
|
|
always @(posedge clk_sys or negedge async_rst_n) begin
|
|
if (!async_rst_n) sync_ff <= 2'b00;
|
|
else sync_ff <= {sync_ff[0], 1'b1};
|
|
end
|
|
|
|
assign rst = ~sync_ff[1];
|
|
|
|
endmodule
|