micheleandClaude Sonnet 5
59901a4905
Closes the flash #1 RTL gap flagged in DEC-0041: real, unmodified V1 subsystem (flash_slot_manager.v/flash_copy_engine.v/spi_flash_master.v/ crc32.v) now instantiated in fpga_neural_v2_top.v, bridged to the AR memory bus via a new flash_mem_adapter.v (byte<->word, matches nms_memory_manager_stream_wide.v's own real masking convention), and commandable over SPI via a new spi_host_bridge.v opcode (OP_FLASH_CMD, 0x30) using the same byte-counting idiom as OP_WRITE_JOB. Real balls now in the LPF: flash_sclk=B2, flash_mosi=E2, flash_miso=F2, flash_cs_n=F3. New tb_flash_integration_smoke.v: real SPI-triggered OP_FLASH_READ_BLOCK verified bit-exact (64/64 bytes) against a real V1 flash_model.v instance, through the new adapter and the widened (2->3 port) host-arb arbiter; WRITE_JOB regression confirms the new 3rd port doesn't disturb existing traffic. Full existing regression re-run clean: D-Stress N=4/ N=8 (bit-exact + data_ready PASS), board-level smoke test (11/11), isolated spi_host_bridge test (18/18). Honest, disclosed finding: a full 8-seed P&R re-verification shows N_SLOTS=4 @ 64MHz regressed from 8/8 to 3/8 PASS (worst 60.18MHz). Root cause traced via the real critical-path report: the SAME pre-existing arbiter-to-sdram-backend bottleneck already documented all session, made worse by flash's added die-area placement pressure -- not a new path through the flash logic itself. N_SLOTS=8 essentially unchanged (6/8, was 5/8). See decisions.log DEC-0042 for full detail and open decision points. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
85 lines
3.2 KiB
Verilog
85 lines
3.2 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// FLASH_MEM_ADAPTER -- bridges flash_slot_manager.v's real, unmodified
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// V1 "Port D" (PSRAM-style byte interface: d_req/d_wr/d_addr/d_wdata/
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// d_rdata/d_ready, byte-addressed, 8-bit signed data) to V2's real AR-
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// port convention (word address, 16-bit data, lb_n/ub_n byte lane
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// masking) used by slot_mem_arbiter.v's clients.
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//
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// Byte<->word convention matches nms_memory_manager_stream_wide.v's
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// own real, already-verified result-writeback logic EXACTLY (not
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// invented): word_addr = byte_addr[ADDR_WIDTH-1:1], byte_addr[0]==0
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// selects the LOWER lane (lb_n=0,ub_n=1), byte_addr[0]==1 selects the
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// UPPER lane (lb_n=1,ub_n=0); write data is replicated to both halves
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// of the 16-bit word, the mask picks which half the SDRAM controller
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// actually writes.
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//
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// Simple valid/ready passthrough: request held (s_req) from issue
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// until the arbiter/backend returns s_ready, matching the same
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// "hold, don't pulse" idiom already used throughout this project
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// (nms_memory_manager_stream_wide.v, spi_host_bridge.v's own mem_req).
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// ================================================================
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module flash_mem_adapter #(
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parameter ADDR_WIDTH = 26, // AR-side word-address bus width
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parameter BYTE_ADDR_WIDTH = 26 // flash_slot_manager's own PSRAM_ADDR_WIDTH
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)(
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input wire clk,
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input wire rst,
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// ---- flash_slot_manager's own real "Port D" ----
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input wire d_req,
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input wire d_wr,
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input wire [BYTE_ADDR_WIDTH-1:0] d_addr,
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input wire signed [7:0] d_wdata,
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output reg signed [7:0] d_rdata,
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output reg d_ready,
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// ---- AR-port-style client, into slot_mem_arbiter.v ----
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output reg s_req,
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output reg s_wr,
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output reg [ADDR_WIDTH-1:0] s_addr,
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output reg [15:0] s_wdata,
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output reg s_lb_n,
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output reg s_ub_n,
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input wire [15:0] s_rdata,
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input wire s_ready
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);
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reg pending;
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reg lane;
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always @(posedge clk) begin
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if (rst) begin
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s_req <= 1'b0;
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s_wr <= 1'b0;
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s_addr <= {ADDR_WIDTH{1'b0}};
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s_wdata <= 16'h0;
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s_lb_n <= 1'b1;
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s_ub_n <= 1'b1;
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d_ready <= 1'b0;
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d_rdata <= 8'sd0;
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pending <= 1'b0;
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lane <= 1'b0;
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end else begin
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d_ready <= 1'b0;
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if (!pending && d_req) begin
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s_req <= 1'b1;
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s_wr <= d_wr;
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s_addr <= d_addr[BYTE_ADDR_WIDTH-1:1];
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lane <= d_addr[0];
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s_wdata <= d_addr[0] ? {d_wdata, 8'h00} : {8'h00, d_wdata};
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s_lb_n <= d_addr[0] ? 1'b1 : 1'b0;
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s_ub_n <= d_addr[0] ? 1'b0 : 1'b1;
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pending <= 1'b1;
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end else if (pending && s_ready) begin
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s_req <= 1'b0;
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d_rdata <= lane ? s_rdata[15:8] : s_rdata[7:0];
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d_ready <= 1'b1;
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pending <= 1'b0;
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end
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end
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end
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endmodule
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