micheleandClaude Sonnet 5
81a9619214
hardware/v1/ was created (dc0b331) as a frozen snapshot of the V1
project that then lived at the repo root (rtl/, sim/, synth/, tools/,
docs/). Root received zero further commits to those files after the
freeze -- confirmed byte-identical to the hardware/v1/ copy for every
file removed here. Root was the "before", hardware/v1/ is the
curated, canonical "after".
Removed (all verified exact-hash duplicates of hardware/v1/ content):
- rtl/ (20 files, 100% covered by hardware/v1/rtl/)
- tools/{netasm,pinout,run_regression.py,flash_catalog,validation,
fpga_benchmark.py} (19 files, 100% covered by hardware/v1/tools/;
tools/neural_sim/ kept -- unique, post-freeze, no counterpart)
- sim/*.v (47 testbenches, 100% covered by hardware/v1/sim/; the
~38 remaining sim/ entries are compiled binaries and .vcd
waveform dumps, left as a separate cleanup decision)
- synth/ecp5/{p2,p4,p8,post_fix_verify} (25 files, exact duplicates
of hardware/v1/synthesis/; the other ~84 synth/ecp5/* experiment
build directories are historical artifacts never carried into the
freeze, left as a separate decision)
- WORKLOG.md (duplicate of hardware/v1/docs/WORKLOG.md)
- docs/{FPGA-Neural-Datapatch-Benchmark,FPGA-Neural-Hardware-Design,
FPGA-NeuralNetwork-Engine}.md, docs/validation/*.md (18 files),
docs/FPGA-Neural-Datasheet-{EN,IT}.pdf -- all exact duplicates of
hardware/v1/docs/ content
- hardware/v1/docs/DatasheetLatex/ (24 files) -- exact duplicate of
hardware/v2/docs/datasheet/files/docs/datasheet/en/ (discovered
during this audit; not the same DatasheetLatex already removed
from hardware/v2/docs/ in an earlier commit)
Moved (genuine, unique, post-freeze V2 content -- not duplicated
anywhere, just living in the wrong/legacy root docs/ location):
- docs/architecture/*.md -> hardware/v2/docs/architecture/
- docs/pinouts.md, docs/FPGA_NEURAL_V2_DATASHEET.md,
docs/FPGA_NEURAL_V2_SCHEMATIC.md,
docs/FPGA-Neural-V2-Datasheet-EN.pdf -> hardware/v2/docs/
Left untouched (separate decisions, not part of this cleanup):
- docs/FPGA-Neural-Flash-Subsystem-Verification.md, docs/
v2-description.md -- orphaned root-only content, no duplicate
found anywhere, but also not part of the reviewed plan
- synth/ecp5/* experiment dirs and sim/*_sim + sim/*.vcd build
artifacts -- not literal duplicates, flagged as candidates for a
future, separate cleanup pass
Verified no functional breakage: grepped all remaining scripts/docs
for references to every removed path -- only prose/comment mentions
found, no executable imports or build-script paths broken.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
161 lines
6.7 KiB
Markdown
161 lines
6.7 KiB
Markdown
# FPGA-Neural V2 — Reference Schematic (textual)
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**No KiCad schematic was generated this session.** No RTL-to-schematic
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or netlist-to-KiCad automation tool is available in this environment,
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and the project's own separate, pre-existing KiCad PCB directory
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(`FPGA-Neural/FPGA-Neural/FPGA-Neural/`) is an unrelated, independently
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tracked project (its own nested `.git`, near-empty as of last check) —
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it was not touched, and this document does not assume its contents.
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This is a textual/ASCII reference schematic: a real starting point for
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PCB capture, not a substitute for one. All ball assignments below are
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the real, P&R-verified ones from `hardware/v2/constraints/
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v2_unified.lpf` (STEP19) unless marked otherwise.
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## 1. Top-level block diagram
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```
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+---------------------------+
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| HOST MCU |
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| SPI |
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+------------+----------------+
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v
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+----------------------------------------------------------+
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| ECP5 FPGA (LFE5U-45F-8BG381) |
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| |
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| +--------------+ +---------------------------+ |
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| | SPI Host |---->| Register / Control | |
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| | Bridge | | (job registration) | |
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| +--------------+ +-------------+-------------+ |
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| | |
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| +-------------v-------------+ |
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| | Neural Accelerator (N=4) | |
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| | Processor 0..3 | |
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| +-------------+-------------+ |
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| | |
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| +-------------v-------------+ |
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| | Unified SDRAM Backend | |
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| +-------------+-------------+ |
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+----------------------------------------------------------+
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16-bit SDRAM bus
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v
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+----------------------------+
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| AS4C4M16SA-6TIN |
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| Weights / Activations / |
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| Results |
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+----------------------------+
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16 MHz osc --> ECP5 PLL (EHXPLLL) --> 64 MHz system clock
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Power rails --> POR/supervisor --> FPGA reset, SDRAM init
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Configuration flash + JTAG connector (see 5/6)
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```
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## 2. SDRAM connection table (real, P&R-verified balls)
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| Signal | Ball | Bank | I/O std (assumed) | Direction |
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|---|---|---|---|---|
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| CLK (shared w/ system clk) | H5 | — | LVCMOS33 | FPGA -> SDRAM |
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| CKE | B5 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| CS_N | C5 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| RAS_N | C4 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| CAS_N | A3 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| WE_N | B3 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| BA[0] | E4 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| BA[1] | C3 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| A[0..11] | D5,D3,F4,E5,E3,F5,A2,B1,C2,C1,D2,D1 | 7 | LVCMOS33 | FPGA -> SDRAM |
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| DQ[0..15] | E1,G5,H3,J5,K3,K2,H1,J1,K1,K4,L4,L5,M5,M4,N4,N5 | 7/6 | LVCMOS33 | bidirectional |
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| DQM[0..1] | P5,N3 | 6 | LVCMOS33 | FPGA -> SDRAM |
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Full source: `hardware/v2/constraints/v2_unified.lpf`. LVCMOS33 is
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assumed to match the SDRAM's own real 3.3V requirement and matches
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banks 6/7's real VCCIO range per `docs/pinouts.md` — not yet
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independently cross-checked at the schematic/PCB level (WARNING, not
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BLOCKER).
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## 3. Clock schematic
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```
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16MHz OSC ---> CLKI (H5, reused from V1's own real LPF)
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+-----v------+
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| EHXPLLL | CLKI_DIV=1, CLKFB_DIV=4, CLKOP_DIV=9
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| (hard IP) | FEEDBK_PATH=CLKOP, VCO=576MHz
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+-----+------+
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| CLKOP = 64MHz
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v
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FPGA system clock (feeds compute, SDRAM ctrl, SPI bridge)
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+-----v------+
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| reset_sync | <-- ext POR (active-low) + PLL LOCK
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+-----+------+
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v
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rst (sync-deassert, feeds every synchronous block)
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```
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Oscillator part number: **TBD** (not selected this session — a real
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16MHz, 3.3V HCMOS clock oscillator in a standard SMD package is the
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intended class of part; no specific manufacturer/part number is
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claimed without a real datasheet lookup performed this session).
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## 4. Power schematic (rails only — no regulator parts selected)
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```
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3.3V/1.1V/2.5V rails (regulators: TBD)
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| | |
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v v v
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VCCIO VCC(core) VCCAUX
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(banks (real ball (real ball
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6/7=SDRAM cluster, cluster,
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I/O, etc) see see
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POWER_ARCH POWER_ARCH
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.md) .md)
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v
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SDRAM VDD/VDDQ (3.3V, DATASHEET VALUE per AS4C4M16SA-6TIN)
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```
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Full rail table, decoupling guidance, and current-budget status:
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`hardware/v2/docs/POWER_ARCHITECTURE.md` (unchanged this step — no new
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power work performed).
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## 5. Configuration / JTAG schematic
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```
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FPGA
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|-- TDI/TDO/TCK/TMS --> JTAG connector (standard pinout, always
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| available regardless of boot mode)
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|-- PROGRAMN/INITN/DONE/CCLK --> configuration flash (part: TBD) or
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JTAG-only bring-up (decision: OPEN)
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```
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No configuration-flash part has been selected; JTAG-only bring-up
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remains a valid fallback and is documented as such in
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`hardware/v2/docs/CONFIGURATION.md`-equivalent content inside
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`OPEN_ITEMS.md` (a dedicated `CONFIGURATION.md` was not created this
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round — tracked as an open item, not silently dropped).
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## 6. Host interface schematic
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```
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Host MCU --SPI--> FPGA: spi_sclk, spi_mosi, spi_miso, spi_cs_n
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```
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No ball assignment exists yet for these 4 signals (the board-level
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top was not run through P&R this session — see the datasheet's own
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§11 Limitations). Pull-up on `spi_cs_n` (idle-high) is the standard,
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expected design decision for a single-master SPI bus; not yet placed
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in any real LPF.
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## 7. What this schematic deliberately does NOT claim
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- No KiCad artifact. No PCB. No fabricated board.
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- No ball assignment for the new SPI/oscillator/reset pins (P&R not
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run against the new board-level top this session, since the design
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has a known, unresolved functional defect — see errors.log
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ERR-0025 Part B).
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- No regulator, flash, or connector part numbers.
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This document is a real, honest starting point for PCB capture, not a
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finished schematic.
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