FPGA-Neural

T

micheleandClaude Sonnet 5 4b5cd4e558 fix: rewrite layer_tb and neuron_parallel_tb for current INT8 architecture

Both testbenches instantiated their DUTs with a FRAC_BITS parameter and
Q8.8 fixed-point 16-bit values, which no longer exist in rtl/neuron_parallel.v
(now plain INT8, DATA_WIDTH=8, hardcoded +127 saturation, ReLU-only clamp).
This made both tests fail elaboration ("parameter FRAC_BITS not found").

Rewrote both benches with integer INT8 stimuli and expectations matching
the current core (no RTL changes): neuron_parallel_tb covers a mixed
vector, ReLU, positive saturation, and mixed values with a boundary
negative bias; layer_tb covers 8 neurons exercising scale, ReLU,
saturation, bias-only, and a sparse weight pattern across groups.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt

2026-09-02 14:16:34 +02:00

docs

working with memory

2026-09-02 13:09:20 +02:00

rtl

working with memory

2026-09-02 13:09:20 +02:00

sim

fix: rewrite layer_tb and neuron_parallel_tb for current INT8 architecture

2026-09-02 14:16:34 +02:00

synth/ecp5

working with memory

2026-09-02 13:09:20 +02:00

WORKLOG.md

fix: rewrite layer_tb and neuron_parallel_tb for current INT8 architecture

2026-09-02 14:16:34 +02:00