micheleandClaude Sonnet 5
4acc669d43
Adds n16_system_ddr3_top.v, directly adapted from n2_system_ddr3_top.v's own proven structure: same real MIG, spi_host_bridge_v3.v, flash_spi_ master.v, host_mem_bridge.v, all completely unmodified (confirms EXP-0090's zero-protocol-change finding holds at full N=16 scale). The real differences: neural_director_grouped.v replaces neural_director_ packed.v, 4x systolic_group.v replace 2x packed_slot.v, and the shared arbiter grows to a real 21-way NUM_REQ (4 group weight-fetch + 16 PE activation/writeback + 1 host_mem_bridge). Real synthesis-only result: 0 Errors, 0 Critical Warnings, 128 DSP48E1 of 240 (53.33%) -- an exact real match to docs/ARCHITECTURE_ANALYSIS.md S5.6's own original brainstorm DSP projection, now confirmed by real synthesis instead of estimated. Found and root-caused a real Vivado project quirk (not an RTL bug -- verified separately via a clean Icarus elaboration with stub modules for mig_7series_0/STARTUPE2): a fresh add_files + update_compile_order didn't make synth_design -top <newmodule> find the module. Fixed by explicitly setting the fileset's own top property before synth_design. CLAUDE.md updated with this as the real, confirmed procedure for adding any future brand-new top-level module. Honestly scoped: synthesis-only (connectivity/width correctness), NOT yet a real functional xsim test and NOT yet real P&R timing -- both real, disclosed next steps. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.