micheleandClaude Sonnet 5
1ce78dff6e
EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).
EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
261 lines
12 KiB
Verilog
261 lines
12 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0057 -- real measured comparison: weight-stationary layer reuse
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// (layer_weight_buffer.v, double-buffered, background-prefetched)
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// vs the zero-reuse D-Stress-style pattern (every read is its own
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// independent external fetch), BOTH driven through the SAME real,
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// already-verified open-row SDR SDRAM controller (sdram_controller_
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// openrow.v, EXP-0054) and behavioral chip model (sdram_model.v) --
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// no DDR3, no clock change, the exact hardware this project already
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// has. Answers directly: does weight reuse alone (no new memory
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// hardware) close enough of the gap that DDR3 stops being necessary
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// for a workload class that actually has reuse (e.g. a CNN layer),
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// as opposed to D-Stress's own deliberately zero-reuse worst case?
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//
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// SAME total useful-byte-consumption for both cases (fair
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// comparison): L=16 "layers" x M=16 reuses x LAYER_DEPTH=128 bytes =
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// 32768 total byte-reads -- identical to D-Stress's own 256x128=32768
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// total bytes this whole project has been benchmarked against all
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// session.
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// REUSE case: L x LAYER_DEPTH = 2048 bytes actually fetched from
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// SDRAM (each layer's weights fetched ONCE, reused
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// M times from the local double buffer).
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// ZERO-REUSE case: L x M x LAYER_DEPTH = 32768 bytes fetched (every
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// single read is independent, matching D-Stress).
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam ALIGN_BITS = $clog2(BURST_LEN);
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam LAYER_DEPTH = 128; // bytes/layer weight block (matches P_IN*MAX_TILES=8*16 tile convention)
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localparam L = 16; // number of layers
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localparam M = 16; // reuses per layer (e.g. spatial positions a filter slides across)
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localparam WORDS_PER_LAYER = LAYER_DEPTH/2; // sdram_controller word=16-bit
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localparam BURSTS_PER_LAYER = LAYER_DEPTH/(2*BURST_LEN); // 16-byte (8-word) transactions per layer
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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integer cyc;
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always @(posedge clk) if (!rst) cyc <= cyc + 1;
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// ================= shared physical SDRAM (real open-row controller) =================
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reg ctrl_req, ctrl_wr;
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reg [ADDR_WIDTH-1:0] ctrl_addr;
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reg [16*BURST_LEN-1:0] ctrl_wdata;
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reg [2*BURST_LEN-1:0] ctrl_wmask;
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wire [16*BURST_LEN-1:0] ctrl_rdata;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller_openrow #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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task automatic sdram_write_burst(input [ADDR_WIDTH-1:0] word_addr, input [16*BURST_LEN-1:0] data);
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begin
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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ctrl_req = 1'b1; ctrl_wr = 1'b1; ctrl_addr = word_addr; ctrl_wdata = data; ctrl_wmask = {(2*BURST_LEN){1'b0}};
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@(posedge clk); ctrl_req = 1'b0;
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while (!ctrl_ready) @(posedge clk);
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end
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endtask
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task automatic sdram_read_burst(input [ADDR_WIDTH-1:0] word_addr, output [16*BURST_LEN-1:0] data);
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begin
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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ctrl_req = 1'b1; ctrl_wr = 1'b0; ctrl_addr = word_addr; ctrl_wmask = {(2*BURST_LEN){1'b0}};
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@(posedge clk); ctrl_req = 1'b0;
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while (!ctrl_ready) @(posedge clk);
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data = ctrl_rdata;
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end
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endtask
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// ================= layer_weight_buffer under test =================
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reg fill_we;
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reg [$clog2(LAYER_DEPTH)-1:0] fill_addr;
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reg [7:0] fill_data;
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reg fill_done;
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reg [$clog2(LAYER_DEPTH)-1:0] rd_addr;
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wire [7:0] rd_data;
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reg consume_done;
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wire active_sel, swapped;
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layer_weight_buffer #(.DATA_WIDTH(8), .LAYER_DEPTH(LAYER_DEPTH)) u_lwb (
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.clk(clk), .rst(rst),
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.fill_we(fill_we), .fill_addr(fill_addr), .fill_data(fill_data), .fill_done(fill_done),
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.rd_addr(rd_addr), .rd_data(rd_data), .consume_done(consume_done),
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.active_sel(active_sel), .swapped(swapped)
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);
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integer errors, tests;
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// pre-load SDRAM with L distinct layer patterns, at word address layer_idx*WORDS_PER_LAYER
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task automatic preload_sdram_layers;
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integer li, bi;
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reg [16*BURST_LEN-1:0] burst_data;
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integer wb;
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begin
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for (li = 0; li < L; li = li + 1) begin
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for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin
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for (wb = 0; wb < BURST_LEN; wb = wb + 1)
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burst_data[wb*16 +: 16] = {8'(8'h20+li), 8'(bi*BURST_LEN+wb)};
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sdram_write_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data);
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end
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end
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end
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endtask
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// fetch layer li's weights (bulk sequential, BURSTS_PER_LAYER transactions)
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// into the layer_weight_buffer's inactive side
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task automatic prefetch_layer(input integer li);
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integer bi, wb;
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reg [16*BURST_LEN-1:0] burst_data;
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begin
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for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin
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sdram_read_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), burst_data);
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for (wb = 0; wb < BURST_LEN; wb = wb + 1) begin
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@(posedge clk);
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fill_we = 1'b1;
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fill_addr = (bi*BURST_LEN + wb) & (2*BURST_LEN-1) | (bi*2*BURST_LEN); // byte index within layer
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fill_addr = bi*(2*BURST_LEN) + wb*2; // low byte of word wb
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fill_data = burst_data[wb*16 +: 8];
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@(posedge clk);
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fill_addr = bi*(2*BURST_LEN) + wb*2 + 1; // high byte of word wb
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fill_data = burst_data[wb*16+8 +: 8];
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end
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end
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@(posedge clk); fill_we = 1'b0;
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fill_done = 1'b1; @(posedge clk); fill_done = 1'b0;
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end
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endtask
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task automatic consume_layer_check(input integer li, input integer errors_before, output integer errors_after);
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integer r, k;
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reg [7:0] expected;
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begin
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errors_after = errors_before;
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for (r = 0; r < M; r = r + 1) begin
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for (k = 0; k < LAYER_DEPTH; k = k + 1) begin
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rd_addr = k[$clog2(LAYER_DEPTH)-1:0];
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#1;
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tests = tests + 1;
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expected = 8'(8'h20+li) ; // high byte of the 16-bit word pattern for even k, low byte pattern for odd k -- see preload
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// preload packed {8'h20+li, byte_idx} per WORD (16-bit): low byte = byte_idx, high byte = 8'h20+li
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if (k[0] == 1'b0) expected = {1'b0, k[7:1]}; // low byte of word = WORD index (bi*BURST_LEN+wb), i.e. k/2 -- see preload_sdram_layers
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else expected = 8'(8'h20+li); // high byte of word = layer tag
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if (rd_data !== expected) begin
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$display("FAIL layer=%0d reuse=%0d k=%0d: expected %h got %h", li, r, k, expected, rd_data);
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errors_after = errors_after + 1;
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end
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@(posedge clk);
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end
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end
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consume_done = 1'b1; @(posedge clk); consume_done = 1'b0;
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end
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endtask
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integer li_i;
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integer t0, total_cycles_reuse, total_cycles_zeroreuse;
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// zero-reuse baseline: L*M independent reads, each LAYER_DEPTH bytes,
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// NO local buffering -- every single "reuse" goes straight to SDRAM,
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// matching D-Stress's own access pattern exactly (through the SAME
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// real open-row controller).
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task automatic zero_reuse_baseline;
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integer li, r, bi;
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reg [16*BURST_LEN-1:0] junk;
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begin
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for (li = 0; li < L; li = li + 1) begin
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for (r = 0; r < M; r = r + 1) begin
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for (bi = 0; bi < BURSTS_PER_LAYER; bi = bi + 1) begin
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sdram_read_burst((li*WORDS_PER_LAYER + bi*BURST_LEN), junk);
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end
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end
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end
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end
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endtask
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initial begin
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errors = 0; tests = 0; cyc = 0;
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rst = 1; ctrl_req = 0; ctrl_wr = 0; ctrl_addr = 0; ctrl_wdata = 0; ctrl_wmask = 0;
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fill_we = 0; fill_addr = 0; fill_data = 0; fill_done = 0; rd_addr = 0; consume_done = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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$display("=== preload SDRAM with %0d distinct layer patterns ===", L);
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preload_sdram_layers;
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$display("=== REUSE case correctness pass: %0d layers x %0d reuses, double-buffered background prefetch (data check only, not timed) ===", L, M);
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prefetch_layer(0);
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consume_done = 1'b1; @(posedge clk); consume_done = 1'b0; // trigger initial swap
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for (li_i = 0; li_i < L; li_i = li_i + 1) begin
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fork
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consume_layer_check(li_i, errors, errors);
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begin
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if (li_i+1 < L) prefetch_layer(li_i+1);
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end
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join
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end
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$display(" correctness: %0d/%0d, %0d errors", tests-errors, tests, errors);
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// ---- FAIR timing comparison: measure ONLY the real SDRAM
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// fetch cost in each case (the actual question this benchmark
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// exists to answer -- how much does reuse reduce dependence on
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// external memory bandwidth). Compute-side consumption cost is
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// deliberately excluded from BOTH measurements here -- it is
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// identical in both cases (same neural_processor.v pipeline
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// rate regardless of where weights come from) and including it
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// asymmetrically was a real bug in an earlier version of this
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// testbench (see EXP-0057 writeup). ----
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$display("=== REUSE case: pure SDRAM fetch time for %0d layers (%0d bytes total) ===", L, L*LAYER_DEPTH);
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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t0 = cyc;
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for (li_i = 0; li_i < L; li_i = li_i + 1) prefetch_layer(li_i);
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total_cycles_reuse = cyc - t0;
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$display(" REUSE: %0d cycles to fetch %0d bytes from SDRAM (each layer fetched ONCE, reused %0d x locally)",
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total_cycles_reuse, L*LAYER_DEPTH, M);
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$display("=== ZERO-REUSE baseline: pure SDRAM fetch time for %0d bytes (every reuse fetched independently) ===", L*M*LAYER_DEPTH);
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@(posedge clk); while (ctrl_busy) @(posedge clk);
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t0 = cyc;
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zero_reuse_baseline;
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total_cycles_zeroreuse = cyc - t0;
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$display(" ZERO-REUSE: %0d cycles to fetch %0d bytes from SDRAM",
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total_cycles_zeroreuse, L*M*LAYER_DEPTH);
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$display("=== RESULT ===");
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$display(" REUSE case data correctness: %0d/%0d, %0d errors", tests-errors, tests, errors);
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$display(" REAL measured speedup from weight reuse alone (SAME hardware, no DDR3, no clock change): %0f x",
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total_cycles_zeroreuse * 1.0 / total_cycles_reuse);
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if (errors == 0) $display("ALL DATA CHECKS PASSED (tb_layer_reuse_vs_zero_reuse)");
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$finish;
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end
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endmodule
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