micheleandClaude Sonnet 5
49b25f6eb6
Built the real FSM version of EXP-0057's own task-based prefetch pattern (bulk-sequential layer fetch via sdram_controller_openrow.v into layer_weight_buffer.v), so it's an actual instantiable module, not just a simulation convenience. Found and fixed a real bug in the process: cur_fill_addr's own address arithmetic bit-sliced BYTES_PER_BURST down to too few bits (BYTES_PER_BURST[BIDXW-1:0]), silently truncating 16 to 0 -- every burst's bytes landed at fill offset 0-15 instead of their real position, overwriting each other (only each layer's last burst survived). Root cause: misapplied a widening idiom used safely elsewhere in this codebase to a case where the target width was actually too small. Found via a standalone control-flow debug test first, then tracing data once control-flow was cleared. Verified: 8192/8192 bit-exact, 0 errors (was 512/8192 before the fix) through the real controller + SDRAM model, 16 layers. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC