micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
106 lines
3.4 KiB
Markdown
106 lines
3.4 KiB
Markdown
# netasm
|
|
|
|
Host-side assembler for the FPGA-Neural network engine. Compiles a
|
|
small pseudo-assembly description of a network (dense Type #1 or
|
|
sparse-graph Type #2, see the project spec §9) into:
|
|
|
|
- the exact on-disk byte layout (descriptor table + edge blocks,
|
|
spec §4), and
|
|
- the SPI command sequence (`SET_NET_TYPE` / `SET_BASE` / `WRITE_RAM`
|
|
/ `RUN_NETWORK`) needed to load and start it.
|
|
|
|
This is **host tooling only**. Nothing here runs on the FPGA — see
|
|
`rtl/graph_engine.v` and `rtl/spi_engine.v` for the hardware side of
|
|
this protocol.
|
|
|
|
## Grammar
|
|
|
|
```
|
|
; Tipo #1 (dense)
|
|
NET dense
|
|
INPUTS 256
|
|
LAYER 64 relu
|
|
LAYER 16 relu
|
|
LAYER 4 none
|
|
END
|
|
```
|
|
|
|
```
|
|
; Tipo #2 (graph)
|
|
NET graph
|
|
INPUTS 4 ; id 0..3
|
|
NEURON n4 relu bias=2
|
|
CONN 0 w=5
|
|
CONN 1 w=-3
|
|
NEURON n5 none bias=0
|
|
CONN n4 w=2 ; symbolic reference to n4's output
|
|
CONN 2 w=7
|
|
OUTPUT n5
|
|
END
|
|
```
|
|
|
|
`;` starts a comment that runs to end of line. A `CONN <src> w=<int>`
|
|
source is either a bare decimal id (typically one of the network's
|
|
inputs) or the name of a previously declared `NEURON`.
|
|
|
|
For `NET dense`, only layer **sizes** and activations are declared —
|
|
weight/bias **values** come from a trained model and are loaded by
|
|
the host separately (unchanged `WRITE_RAM` flow); netasm's job there
|
|
is layout (address allocation, PARALLEL-alignment validation,
|
|
descriptor table, load/run commands).
|
|
|
|
For `NET graph`, netasm assigns every neuron's signal id (inputs get
|
|
0..N_in-1; every `OUTPUT` neuron is guaranteed the highest ids, as
|
|
required by spec §4.4 — reordering non-output neurons is never
|
|
needed for correctness since the grammar already forces
|
|
before-you-use declaration order), resolves symbolic `CONN`
|
|
references, pads each neuron's edge list to a `PARALLEL` multiple
|
|
with zero-weight edges (spec §2.6 — this is a full, physical
|
|
edge block, not a hint: hardware just streams `n_conn_padded` real
|
|
bytes from PSRAM), and emits the descriptor table + edge blocks +
|
|
load/run command sequence.
|
|
|
|
## Compile-time validation
|
|
|
|
Catches these before the runtime load-time guard in
|
|
`rtl/graph_engine.v` ever would (spec §9's whole point):
|
|
|
|
- `src_id < out_id` (no cycles / forward references)
|
|
- `src_id`, `out_id` < `N_TOTAL`
|
|
- an `OUTPUT` neuron is never used as another neuron's source
|
|
- every `CONN` reference (symbolic or literal) resolves to a real id
|
|
- a neuron's *padded* connection count fits the hardware's
|
|
build-time `MAX_CONN`
|
|
- (dense) every layer's real input count is a `PARALLEL` multiple
|
|
|
|
## Usage
|
|
|
|
```
|
|
python3 tools/netasm/cli.py <input.netasm> -o <out_prefix> \
|
|
[--parallel 8] [--max-conn 32] [--n-total 4096] \
|
|
[--table-base 0x...] [--edges-base 0x...] [--x-base 0x...] \
|
|
[--out-base 0x...] [--buf-b-base 0x...] [--weights-base 0x...]
|
|
```
|
|
|
|
Produces:
|
|
|
|
- `<out_prefix>.frames.bin` — length-prefixed SPI transaction bytes
|
|
(2-byte big-endian length + that many payload bytes, repeated); a
|
|
host driver replays each record by asserting CS, shifting the
|
|
bytes out, then deasserting CS.
|
|
- `<out_prefix>.debug.txt` — human-readable id/address/byte dump for
|
|
review before flashing real hardware.
|
|
|
|
See `examples/graph_example.netasm` and `examples/dense_example.netasm`.
|
|
|
|
## Tests
|
|
|
|
```
|
|
python3 tools/netasm/tests/test_netasm.py -v
|
|
```
|
|
|
|
Includes a byte-exact test against the same worked graph example
|
|
used throughout the RTL testbenches (`sim/graph_format_tb.v`,
|
|
`sim/graph_engine_tb.v`, `sim/spi_neuron_top_graph_tb.v`), plus one
|
|
test per compile-time guard above.
|