micheleandClaude Sonnet 5
a4c080da83
Implements the user's board architecture: config flash wired exclusively to the FPGA, host (ESP32) reaches it only through the FPGA. flash_spi_master.v is a plain byte-wide SPI master using STARTUPE2 to reclaim CCLK after configuration (the real, Xilinx- documented "indirect SPI flash programming" technique, UG470 p94-96). New opcode 0x40 FLASH_XFER in spi_host_bridge_v3.v relays bytes byte-for-byte between host and the physical flash bus -- the host decides the exact SPI NOR command sequence (verified against the real W25Q32JV datasheet), this RTL knows nothing about flash semantics. Found and fixed two real bugs during verification: a byte-assembly off-by-one in flash_spi_master.v, and a genuine protocol-latency bug in the FLASH_XFER opcode's response timing (needed 2 trailing margin bytes, not 1 -- the internal flash transfer doesn't start until the triggering byte finishes, so 1 byte of margin isn't enough). 39/39 tests pass end to end (host SPI -> bridge -> flash_spi_master -> behavioral flash model). Wired into n2_system_ddr3_top.v with real pin constraints (flash_mosi =K17/flash_miso=K18/flash_cs_n=L13, the same pins reserved-but-unused in EXP-0075) and BITSTREAM.CONFIG.PERSIST=FALSE made explicit. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
66 lines
3.6 KiB
Tcl
66 lines
3.6 KiB
Tcl
# ============================================================
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# V3 -- top-level pin/IOSTANDARD constraints for n2_system_ddr3_top.v,
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# real xc7a100tcsg324-2, board is the user's own custom design (bare
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# chip + DDR3, no dev board). DDR3 pins themselves are NOT here --
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# those come from the MIG-generated mig_7series_0.xdc (dictated by
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# the FPGA's internal DDR3 PHY hardware, not a free choice).
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#
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# Verified against the real device via a routed checkpoint query
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# (open_checkpoint + get_package_pins/get_ports on n2_system_ddr3_
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# top_routed.dcp), not guessed from a datasheet table.
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# ============================================================
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# ---- required for flash_spi_master.v to work at all: D00_MOSI/
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# D01_DIN/FCS_B only become ordinary fabric I/O post-configuration
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# when PERSIST is FALSE (the Vivado default -- set explicitly here so
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# this dependency is self-documenting in the constraints, not just a
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# silent default someone could flip later without realizing why).
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set_property BITSTREAM.CONFIG.PERSIST FALSE [current_design]
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# ---- config-flash passthrough (-> flash_spi_master.v, EXP-0077):
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# D00_MOSI/D01_DIN/FCS_B are the SAME physical pins the FPGA's own
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# dedicated Master-SPI config hardware uses AT BOOT to self-load its
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# bitstream -- post-configuration they become ordinary fabric I/O
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# (real Xilinx behavior, PERSIST=FALSE, the Vivado default) and this
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# design deliberately reclaims them for the flash_spi_master.v bridge
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# (the board wires the config flash EXCLUSIVELY to the FPGA -- see
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# that module's own header). CCLK is NOT constrained here -- it's
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# driven via STARTUPE2 internally, never a plain top-level port.
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set_property PACKAGE_PIN K17 [get_ports flash_mosi]
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set_property PACKAGE_PIN K18 [get_ports flash_miso]
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set_property PACKAGE_PIN L13 [get_ports flash_cs_n]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_miso]
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set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]
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# ---- EMCCLK/RDWR_B/CSI_B (bank 14): not used by this design at all
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# (this project's Master SPI config mode never needed them -- they're
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# only relevant to modes this board doesn't use, e.g. BPI or Quad-SPI
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# extra data lines) -- PROHIBITed so Vivado's auto-placement never
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# lands an unrelated port there by accident (it already had once,
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# before this constraint existed, on a result-data bit).
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set_property PROHIBIT true [get_package_pins {L16 R16 V15}]
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# ---- neural-processor management SPI (-> spi_host_bridge_v3.v):
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# job submission + register file. Bank 15, column A/B (package edge,
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# physically adjacent pins for short/easy PCB routing), well clear of
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# both DDR3 (banks 34/35) and the reserved config-flash pins above.
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# IOSTANDARD assumes bank 15 is powered at 3.3V on the custom board --
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# change to match whatever VCCO the user's own power plan uses for
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# that bank.
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set_property PACKAGE_PIN A15 [get_ports sclk]
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set_property PACKAGE_PIN B16 [get_ports mosi]
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set_property PACKAGE_PIN B17 [get_ports miso]
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set_property PACKAGE_PIN A16 [get_ports cs_n]
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set_property IOSTANDARD LVCMOS33 [get_ports sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports mosi]
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set_property IOSTANDARD LVCMOS33 [get_ports miso]
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set_property IOSTANDARD LVCMOS33 [get_ports cs_n]
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# ---- sys_rst: not part of the DDR3 MIG's own pin set (that's
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# sys_rst too, but MIG's XDC only constrains the DDR3-facing timing,
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# not necessarily IOSTANDARD for every board variant) -- pin left to
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# auto-placement for now (low pin-count, no real board decision yet
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# on where the reset source sits); explicitly constrain once the PCB
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# layout for the reset circuit (button/supervisor IC) is decided.
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