micheleandClaude Sonnet 5
ee5a68f6e6
EXP-0053: sdram_cdc_bridge.v decouples the SDRAM clock (115.2MHz, real value derived from the board's own existing PLL VCO=576MHz, verified via ecppll) from the 64MHz compute domain. Isolated: 137/137 tests, 0 errors, but real measured speedup is only 1.095x (not the naive 1.8x clock-ratio estimate) -- the CDC handshake's own synchronizer round-trip is a fixed per-transaction tax. EXP-0054: sdram_controller_openrow.v implements the page-hit/ keep-row-open optimization sdram_controller.v's own header had always deferred. weight_prefetch_engine_wide.v's real production traffic is strictly sequential per job and mostly stays within one SDRAM row -- closing/reopening it every tile (today's fixed auto-precharge policy) wastes tRP+tRCD for no reason. Isolated: 154/154 tests, 0 errors, 0 protocol violations (including the new refresh-while-row-open hazard, fixed via an explicit precharge-before-refresh path). Real measured speedup on the actual sequential access pattern: 1.141x. EXP-0055: composed both, then integrated into the real D-Stress benchmark (N=4/N=8, 256/256 bit-exact in every config). Result: open-row ALONE gives a real, consistent ~5% cycle-count improvement (47445/47468 vs baseline 49927/49909). CDC alone is a real ~8% REGRESSION. Combined is still a ~4% regression -- the CDC's fixed tax is paid on every transaction regardless of row-hit, and real D-Stress traffic interleaves weight-fetch/activation-result access far more than the isolated same-row test exercised, so open-row's real saving doesn't offset it. Decision: do not adopt the CDC approach; open-row alone is the disclosed, real win worth considering for production next, pending an explicit go-ahead (not applied to the real board top in this commit -- all additive, existing production RTL untouched). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
372 lines
16 KiB
Verilog
372 lines
16 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0054 -- isolated correctness + real measured speedup for
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// sdram_controller_openrow.v. Two DUTs share the exact same
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// transaction sequence, each with its own sdram_model.v instance:
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// dut_base : sdram_controller.v (today's real, unchanged baseline
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// -- always auto-precharges).
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// dut_openrow : sdram_controller_openrow.v (new, page-hit policy).
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//
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// Covers:
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// 1) correctness battery (write->read, sequential/bank-sweep/
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// pseudo-random), bit-exact vs the same golden pattern, on BOTH
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// DUTs.
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// 2) SAME-ROW consecutive access (the real production pattern:
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// weight_prefetch_engine_wide.v's own strictly sequential tile
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// stream) -- bit-exact AND real measured cycle savings vs
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// baseline.
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// 3) DIFFERENT-ROW access immediately after a row is open -- must
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// stay bit-exact and NOT regress vs baseline (on-demand precharge
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// pays the same total cost, just deferred).
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// 4) explicit read-after-read / write-after-read / read-after-write
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// / write-after-write SAME-ROW turnaround sequences -- the one
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// hazard class sdram_model.v does NOT itself assert (no tCCD/
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// tRTW/tWTR check in that model -- see sdram_controller_
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// openrow.v's own header) -- checked here for DATA correctness,
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// which is the strongest check available without a turnaround-
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// timing-aware reference model.
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// 5) refresh spanning while a row is open -- watches for ANY
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// VIOLATION/WARNING from sdram_model.v (this project's own real
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// command-sequence checker) across many iterations, specifically
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// exercising the new precharge-before-refresh path.
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// 6) REAL measured total-cycle comparison over a long, strictly
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// sequential same-row run -- the actual production access
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// pattern (weight_prefetch_engine_wide.v), the number this
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// experiment exists to produce.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam ALIGN_BITS = (BURST_LEN<=1) ? 0 : $clog2(BURST_LEN);
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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integer cyc;
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always @(posedge clk) if (!rst) cyc <= cyc + 1;
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function automatic [BANK_BITS-1:0] bank_of;
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input [ADDR_WIDTH-1:0] a;
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begin
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bank_of = a[ALIGN_BITS +: BANK_BITS];
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end
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endfunction
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function automatic [ROW_BITS-1:0] row_of;
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input [ADDR_WIDTH-1:0] a;
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begin
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row_of = a[ALIGN_BITS+BANK_BITS +: ROW_BITS];
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end
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endfunction
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// ================= DUT BASE (today's real baseline) =================
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reg reqA, wrA;
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reg [ADDR_WIDTH-1:0] addrA;
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reg [16*BURST_LEN-1:0] wdataA;
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reg [2*BURST_LEN-1:0] wmaskA;
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wire [16*BURST_LEN-1:0] rdataA;
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wire readyA, busyA;
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wire cke_A, cs_A, ras_A, cas_A, we_A;
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wire [BANK_BITS-1:0] ba_A;
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wire [ROW_BITS-1:0] a_A;
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wire [15:0] dq_A;
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wire [1:0] dqm_A;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) dut_base (
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.clk(clk), .rst(rst),
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.req(reqA), .wr(wrA), .addr(addrA), .wdata(wdataA), .wmask(wmaskA),
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.rdata(rdataA), .ready(readyA), .busy(busyA),
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.sdram_cke(cke_A), .sdram_cs_n(cs_A), .sdram_ras_n(ras_A),
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.sdram_cas_n(cas_A), .sdram_we_n(we_A),
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.sdram_ba(ba_A), .sdram_a(a_A), .sdram_dq(dq_A), .sdram_dqm(dqm_A)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) mem_base (
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.clk(clk), .cke(cke_A), .cs_n(cs_A), .ras_n(ras_A),
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.cas_n(cas_A), .we_n(we_A), .ba(ba_A), .a(a_A), .dq(dq_A), .dqm(dqm_A)
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);
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// ================= DUT OPENROW =================
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reg reqB, wrB;
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reg [ADDR_WIDTH-1:0] addrB;
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reg [16*BURST_LEN-1:0] wdataB;
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reg [2*BURST_LEN-1:0] wmaskB;
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wire [16*BURST_LEN-1:0] rdataB;
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wire readyB, busyB;
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wire cke_B, cs_B, ras_B, cas_B, we_B;
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wire [BANK_BITS-1:0] ba_B;
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wire [ROW_BITS-1:0] a_B;
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wire [15:0] dq_B;
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wire [1:0] dqm_B;
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sdram_controller_openrow #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) dut_openrow (
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.clk(clk), .rst(rst),
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.req(reqB), .wr(wrB), .addr(addrB), .wdata(wdataB), .wmask(wmaskB),
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.rdata(rdataB), .ready(readyB), .busy(busyB),
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.sdram_cke(cke_B), .sdram_cs_n(cs_B), .sdram_ras_n(ras_B),
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.sdram_cas_n(cas_B), .sdram_we_n(we_B),
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.sdram_ba(ba_B), .sdram_a(a_B), .sdram_dq(dq_B), .sdram_dqm(dqm_B)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) mem_openrow (
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.clk(clk), .cke(cke_B), .cs_n(cs_B), .ras_n(ras_B),
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.cas_n(cas_B), .we_n(we_B), .ba(ba_B), .a(a_B), .dq(dq_B), .dqm(dqm_B)
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);
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integer errors, tests;
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task automatic do_txn_A(
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input t_wr,
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input [ADDR_WIDTH-1:0] t_addr,
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input [16*BURST_LEN-1:0] t_wdata,
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output [16*BURST_LEN-1:0] t_rdata,
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output integer t_cycles
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);
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integer t0;
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begin
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@(posedge clk);
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while (busyA) @(posedge clk);
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t0 = cyc;
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reqA = 1'b1; wrA = t_wr; addrA = t_addr; wdataA = t_wdata; wmaskA = {(2*BURST_LEN){1'b0}};
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@(posedge clk);
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reqA = 1'b0;
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while (!readyA) @(posedge clk);
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t_rdata = rdataA;
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t_cycles = cyc - t0;
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end
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endtask
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task automatic do_txn_B(
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input t_wr,
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input [ADDR_WIDTH-1:0] t_addr,
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input [16*BURST_LEN-1:0] t_wdata,
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output [16*BURST_LEN-1:0] t_rdata,
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output integer t_cycles
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);
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integer t0;
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begin
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@(posedge clk);
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while (busyB) @(posedge clk);
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t0 = cyc;
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reqB = 1'b1; wrB = t_wr; addrB = t_addr; wdataB = t_wdata; wmaskB = {(2*BURST_LEN){1'b0}};
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@(posedge clk);
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reqB = 1'b0;
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while (!readyB) @(posedge clk);
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t_rdata = rdataB;
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t_cycles = cyc - t0;
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end
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endtask
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reg [16*BURST_LEN-1:0] gotA, gotB, wpat;
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integer elapsedA, elapsedB;
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task automatic check_word_both(input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
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integer k;
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begin
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for (k = 0; k < BURST_LEN; k = k + 1)
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wpat[k*16 +: 16] = pattern + k[15:0];
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do_txn_A(1'b1, a, wpat, gotA, elapsedA);
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do_txn_A(1'b0, a, {(16*BURST_LEN){1'b0}}, gotA, elapsedA);
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do_txn_B(1'b1, a, wpat, gotB, elapsedB);
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do_txn_B(1'b0, a, {(16*BURST_LEN){1'b0}}, gotB, elapsedB);
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tests = tests + 1;
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if (gotA !== wpat) begin
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$display("FAIL (base) addr=%0d: got=%h expected=%h", a, gotA, wpat);
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errors = errors + 1;
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end
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if (gotB !== wpat) begin
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$display("FAIL (openrow) addr=%0d: got=%h expected=%h", a, gotB, wpat);
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errors = errors + 1;
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end
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if (gotA === wpat && gotB === wpat) begin
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$display("PASS addr=%0d bank=%0d row=%0d: both bit-exact (base=%0d cyc, openrow=%0d cyc)",
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a, bank_of(a), row_of(a), elapsedA, elapsedB);
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end
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end
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endtask
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integer seed;
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integer i;
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reg [ADDR_WIDTH-1:0] rnd_addr;
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initial begin
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errors = 0; tests = 0; cyc = 0; seed = 32'hBADC0FFE;
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rst = 1;
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reqA = 0; wrA = 0; addrA = 0; wdataA = 0; wmaskA = 0;
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reqB = 0; wrB = 0; addrB = 0; wdataB = 0; wmaskB = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk);
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while (busyA || busyB) @(posedge clk);
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$display("=== TEST 1: correctness battery (base vs openrow, same golden pattern) ===");
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check_word_both({ADDR_WIDTH{1'b0}}, 16'hA5A5);
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for (i = 0; i < 8; i = i + 1)
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check_word_both(i*BURST_LEN, 16'h1000 + i);
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for (i = 0; i < 4; i = i + 1)
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check_word_both((i << ALIGN_BITS) + (100 << (ALIGN_BITS+BANK_BITS)), 16'h2000 + i);
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for (i = 0; i < 24; i = i + 1) begin
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rnd_addr = ($random(seed) % ((1<<ADDR_WIDTH)/BURST_LEN)) * BURST_LEN;
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check_word_both(rnd_addr, 16'h3000 + i);
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end
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$display(" TEST 1: %0d/%0d passed so far", tests-errors, tests);
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$display("=== TEST 2: SAME-ROW consecutive tiles (real weight-prefetch pattern) -- real measured savings ===");
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begin : test2
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integer j, N_TILES;
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reg [ADDR_WIDTH-1:0] base_addr, ta;
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reg [16*BURST_LEN-1:0] tw, gA, gB;
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integer eA, eB, totA, totB, t0A, t0B;
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N_TILES = 32; // well within one row (1024 cols / (BURST_LEN=8 words/tile-block) = 128 tile-blocks/row)
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base_addr = (200 << (ALIGN_BITS+BANK_BITS)); // fixed bank/row, sweep column via tile index
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// pre-write all tiles via base (both DUTs must see identical data)
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for (j = 0; j < N_TILES; j = j + 1) begin
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ta = base_addr + (j << ALIGN_BITS);
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tw = {BURST_LEN{16'(16'h4000 + j)}};
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do_txn_A(1'b1, ta, tw, gA, eA);
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do_txn_B(1'b1, ta, tw, gB, eB);
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end
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// now measure a pure sequential READ sweep (this IS the
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// weight_prefetch_engine_wide.v access pattern: strictly
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// increasing tile address, same bank/row throughout)
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@(posedge clk); while (busyA) @(posedge clk);
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t0A = cyc;
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for (j = 0; j < N_TILES; j = j + 1) begin
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ta = base_addr + (j << ALIGN_BITS);
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do_txn_A(1'b0, ta, {(16*BURST_LEN){1'b0}}, gA, eA);
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end
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totA = cyc - t0A;
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@(posedge clk); while (busyB) @(posedge clk);
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t0B = cyc;
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for (j = 0; j < N_TILES; j = j + 1) begin
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ta = base_addr + (j << ALIGN_BITS);
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do_txn_B(1'b0, ta, {(16*BURST_LEN){1'b0}}, gB, eB);
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tests = tests + 1;
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if (gB !== {BURST_LEN{16'(16'h4000 + j)}}) begin
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$display("FAIL TEST2 tile=%0d: openrow got=%h", j, gB);
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errors = errors + 1;
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end
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end
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totB = cyc - t0B;
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$display(" base (always precharge): %0d cycles for %0d sequential same-row reads", totA, N_TILES);
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$display(" openrow (page-hit) : %0d cycles for %0d sequential same-row reads", totB, N_TILES);
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$display(" REAL measured speedup : %0f x", totA * 1.0 / totB);
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end
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$display("=== TEST 3: DIFFERENT-row access right after a row is open -- must not regress vs base ===");
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begin : test3
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reg [ADDR_WIDTH-1:0] addr_row0, addr_row1;
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reg [16*BURST_LEN-1:0] wpat0, wpat1, rd0, rd1;
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integer eA1, eA2, eB1, eB2;
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addr_row0 = (300 << (ALIGN_BITS+BANK_BITS));
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addr_row1 = (301 << (ALIGN_BITS+BANK_BITS)); // different row, same bank
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wpat0 = {BURST_LEN{16'h5000}};
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wpat1 = {BURST_LEN{16'h5001}};
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do_txn_A(1'b1, addr_row0, wpat0, gotA, eA1);
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do_txn_A(1'b1, addr_row1, wpat1, gotA, eA2);
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do_txn_B(1'b1, addr_row0, wpat0, gotB, eB1);
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do_txn_B(1'b1, addr_row1, wpat1, gotB, eB2);
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do_txn_A(1'b0, addr_row0, {(16*BURST_LEN){1'b0}}, rd0, eA1);
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do_txn_B(1'b0, addr_row0, {(16*BURST_LEN){1'b0}}, rd1, eB1);
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tests = tests + 1;
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if (rd0 !== wpat0 || rd1 !== wpat0) begin
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$display("FAIL TEST3 data: base=%h openrow=%h expected=%h", rd0, rd1, wpat0);
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errors = errors + 1;
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end else begin
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$display("PASS TEST3 data: different-row-then-back bit-exact on both, base last-op=%0d cyc openrow last-op=%0d cyc",
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eA1, eB1);
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end
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end
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$display("=== TEST 4: explicit same-row turnaround sequences (R-R, W-R, R-W, W-W) ===");
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begin : test4
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reg [ADDR_WIDTH-1:0] a0, a1;
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reg [16*BURST_LEN-1:0] wp0, wp1, rd0, rd1;
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integer e0, e1;
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a0 = (400 << (ALIGN_BITS+BANK_BITS));
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a1 = a0 + (1 << ALIGN_BITS);
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wp0 = {BURST_LEN{16'h6100}};
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wp1 = {BURST_LEN{16'h6200}};
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do_txn_B(1'b1, a0, wp0, gotB, e0); // seed
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do_txn_B(1'b1, a1, wp1, gotB, e0); // seed
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// R-R
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do_txn_B(1'b0, a0, {(16*BURST_LEN){1'b0}}, rd0, e0);
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do_txn_B(1'b0, a1, {(16*BURST_LEN){1'b0}}, rd1, e1);
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tests = tests + 1;
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if (rd0 !== wp0 || rd1 !== wp1) begin
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$display("FAIL TEST4 R-R: rd0=%h rd1=%h", rd0, rd1); errors = errors + 1;
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end else $display("PASS TEST4 R-R same-row");
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// W-R
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do_txn_B(1'b1, a0, wp1, gotB, e0);
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do_txn_B(1'b0, a0, {(16*BURST_LEN){1'b0}}, rd0, e0);
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tests = tests + 1;
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if (rd0 !== wp1) begin
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$display("FAIL TEST4 W-R: rd0=%h expected=%h", rd0, wp1); errors = errors + 1;
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end else $display("PASS TEST4 W-R same-row");
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// R-W
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do_txn_B(1'b0, a1, {(16*BURST_LEN){1'b0}}, rd1, e0);
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do_txn_B(1'b1, a1, wp0, gotB, e0);
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do_txn_B(1'b0, a1, {(16*BURST_LEN){1'b0}}, rd1, e0);
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tests = tests + 1;
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if (rd1 !== wp0) begin
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$display("FAIL TEST4 R-W: rd1=%h expected=%h", rd1, wp0); errors = errors + 1;
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end else $display("PASS TEST4 R-W same-row");
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// W-W
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do_txn_B(1'b1, a0, wp0, gotB, e0);
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do_txn_B(1'b1, a1, wp1, gotB, e0);
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do_txn_B(1'b0, a0, {(16*BURST_LEN){1'b0}}, rd0, e0);
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do_txn_B(1'b0, a1, {(16*BURST_LEN){1'b0}}, rd1, e0);
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tests = tests + 1;
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if (rd0 !== wp0 || rd1 !== wp1) begin
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$display("FAIL TEST4 W-W: rd0=%h rd1=%h", rd0, rd1); errors = errors + 1;
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end else $display("PASS TEST4 W-W same-row");
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end
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$display("=== TEST 5: refresh spanning while row open (watch for VIOLATION/WARNING above) ===");
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begin : test5
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integer j;
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reg [ADDR_WIDTH-1:0] ta;
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reg [16*BURST_LEN-1:0] tw, gB;
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integer eB;
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ta = (500 << (ALIGN_BITS+BANK_BITS));
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for (j = 0; j < 80; j = j + 1) begin
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tw = {BURST_LEN{16'(16'h7000 + j)}};
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do_txn_B(1'b1, ta, tw, gB, eB);
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do_txn_B(1'b0, ta, {(16*BURST_LEN){1'b0}}, gB, eB);
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tests = tests + 1;
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|
if (gB !== tw) begin
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$display("FAIL TEST5 iter=%0d: got=%h expected=%h", j, gB, tw);
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|
errors = errors + 1;
|
|
end
|
|
end
|
|
$display(" TEST5: 80 same-row write/read pairs completed spanning real tREFI -- check log above for VIOLATION/WARNING");
|
|
end
|
|
|
|
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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|
if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_controller_openrow)");
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|
$finish;
|
|
end
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|
endmodule
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