micheleandClaude Sonnet 5
3dd75e9e0d
int8_memory_access.v byte<->word conversion and byte-lane selection: exhaustive 2048-address test + 6 real read/write round-trips through the FSM handshake. 2054/2054 checks, 0 mismatches, after fixing two bugs in the test harness itself (a same-timestep race reading a non-blocking update one iteration late, and a behavioral memory stub that ignored byte-lane enables on write) -- both documented as test-side, not RTL, issues. memory_interface.v and psram_controller.v not re-verified from scratch: cited against coverage already established/re-confirmed earlier in this same session (page-mode/tCEM against the ISSI datasheet, a real pre-existing power-up request-loss bug found and fixed), re-run clean via the Phase 0 regression harness rather than trusted from WORKLOG text alone. Full regression: 39/39 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
6337 lines
139 KiB
Plaintext
6337 lines
139 KiB
Plaintext
$date
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Fri Sep 4 14:31:28 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 32 ! y_bus [31:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 32 % DATA_WIDTH $end
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$var parameter 32 & N_INPUTS $end
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$var parameter 32 ' N_NEURONS $end
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$var parameter 32 ( PARALLEL $end
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$var reg 32 ) bias_bus [31:0] $end
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$var reg 1 * clk $end
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$var reg 1 + rst $end
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$var reg 1 , start $end
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$var reg 8192 - weights_bus [8191:0] $end
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$var reg 2048 . x_bus [2047:0] $end
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$var integer 32 / errors [31:0] $end
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$var integer 32 0 expected [31:0] $end
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$var integer 32 1 i [31:0] $end
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$scope module dut $end
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$var wire 32 2 bias_bus [31:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 8192 3 weights_bus [8191:0] $end
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$var wire 2048 4 x_bus [2047:0] $end
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$var wire 32 5 y_bus [31:0] $end
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$var wire 4 6 neuron_done [3:0] $end
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$var wire 4 7 neuron_busy [3:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 8 ACC_WIDTH $end
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$var parameter 32 9 DATA_WIDTH $end
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$var parameter 32 : N_INPUTS $end
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$var parameter 32 ; N_NEURONS $end
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$var parameter 32 < PARALLEL $end
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$scope begin GEN_NEURON[0] $end
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$var parameter 2 = n $end
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$scope module u_neuron $end
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$var wire 2 > activation [1:0] $end
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$var wire 8 ? bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 @ final_acc_in_range $end
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$var wire 1 A final_acc_le_zero $end
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$var wire 1 B final_acc_upper_all0 $end
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$var wire 16 C n_inputs_real [15:0] $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 2048 D w_bus [2047:0] $end
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$var wire 2048 E x_bus [2047:0] $end
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$var wire 8 F y_relu [7:0] $end
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$var wire 8 G y_none [7:0] $end
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$var wire 256 H x_group [255:0] $end
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$var wire 256 I w_group [255:0] $end
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$var wire 16 J groups_real [15:0] $end
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$var wire 1 K final_acc_upper_all1 $end
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$var wire 1 L final_acc_sign $end
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$var wire 32 M final_acc [31:0] $end
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$var wire 32 N bias_ext [31:0] $end
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$var wire 32 O acc_next [31:0] $end
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$var parameter 32 P ACC_WIDTH $end
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$var parameter 2 Q ACT_NONE $end
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$var parameter 2 R ACT_RELU $end
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$var parameter 32 S DATA_WIDTH $end
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$var parameter 32 T GROUPS $end
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$var parameter 32 U GROUP_INDEX_WIDTH $end
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$var parameter 32 V N_INPUTS $end
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$var parameter 32 W PARALLEL $end
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$var reg 32 X acc [31:0] $end
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$var reg 1 Y busy $end
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$var reg 1 Z done $end
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$var reg 1 [ finishing $end
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$var reg 3 \ group_index [2:0] $end
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$var reg 8 ] y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 ^ acc_in [31:0] $end
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$var wire 256 _ w_bus [255:0] $end
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$var wire 256 ` x_bus [255:0] $end
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$var wire 32 a acc_out [31:0] $end
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$var parameter 32 b ACC_WIDTH $end
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$var parameter 32 c DATA_WIDTH $end
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$var parameter 32 d PARALLEL $end
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$var parameter 32 e TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 f i $end
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$scope module u_mac $end
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$var wire 32 g acc_in [31:0] $end
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$var wire 8 h w [7:0] $end
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$var wire 8 i x [7:0] $end
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$var wire 32 j product_ext [31:0] $end
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$var wire 16 k product [15:0] $end
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$var wire 32 l acc_out [31:0] $end
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$var parameter 32 m ACC_WIDTH $end
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$var parameter 32 n DATA_WIDTH $end
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$var parameter 64 o PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 p i $end
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$scope module u_mac $end
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$var wire 32 q acc_in [31:0] $end
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$var wire 8 r w [7:0] $end
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$var wire 8 s x [7:0] $end
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$var wire 32 t product_ext [31:0] $end
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$var wire 16 u product [15:0] $end
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$var wire 32 v acc_out [31:0] $end
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$var parameter 32 w ACC_WIDTH $end
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$var parameter 32 x DATA_WIDTH $end
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$var parameter 64 y PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 z i $end
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$scope module u_mac $end
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$var wire 32 { acc_in [31:0] $end
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$var wire 8 | w [7:0] $end
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$var wire 8 } x [7:0] $end
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$var wire 32 ~ product_ext [31:0] $end
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$var wire 16 !" product [15:0] $end
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$var wire 32 "" acc_out [31:0] $end
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$var parameter 32 #" ACC_WIDTH $end
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$var parameter 32 $" DATA_WIDTH $end
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$var parameter 64 %" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 &" i $end
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$scope module u_mac $end
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$var wire 32 '" acc_in [31:0] $end
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$var wire 8 (" w [7:0] $end
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$var wire 8 )" x [7:0] $end
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$var wire 32 *" product_ext [31:0] $end
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$var wire 16 +" product [15:0] $end
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$var wire 32 ," acc_out [31:0] $end
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$var parameter 32 -" ACC_WIDTH $end
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$var parameter 32 ." DATA_WIDTH $end
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$var parameter 64 /" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 0" i $end
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$scope module u_mac $end
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$var wire 32 1" acc_in [31:0] $end
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$var wire 8 2" w [7:0] $end
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$var wire 8 3" x [7:0] $end
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$var wire 32 4" product_ext [31:0] $end
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$var wire 16 5" product [15:0] $end
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$var wire 32 6" acc_out [31:0] $end
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$var parameter 32 7" ACC_WIDTH $end
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$var parameter 32 8" DATA_WIDTH $end
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$var parameter 64 9" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 :" i $end
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$scope module u_mac $end
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$var wire 32 ;" acc_in [31:0] $end
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$var wire 8 <" w [7:0] $end
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$var wire 8 =" x [7:0] $end
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$var wire 32 >" product_ext [31:0] $end
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$var wire 16 ?" product [15:0] $end
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$var wire 32 @" acc_out [31:0] $end
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$var parameter 32 A" ACC_WIDTH $end
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$var parameter 32 B" DATA_WIDTH $end
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$var parameter 64 C" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 D" i $end
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$scope module u_mac $end
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$var wire 32 E" acc_in [31:0] $end
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$var wire 8 F" w [7:0] $end
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$var wire 8 G" x [7:0] $end
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$var wire 32 H" product_ext [31:0] $end
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$var wire 16 I" product [15:0] $end
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$var wire 32 J" acc_out [31:0] $end
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$var parameter 32 K" ACC_WIDTH $end
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$var parameter 32 L" DATA_WIDTH $end
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$var parameter 64 M" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 N" i $end
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$scope module u_mac $end
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$var wire 32 O" acc_in [31:0] $end
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$var wire 8 P" w [7:0] $end
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$var wire 8 Q" x [7:0] $end
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$var wire 32 R" product_ext [31:0] $end
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$var wire 16 S" product [15:0] $end
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$var wire 32 T" acc_out [31:0] $end
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$var parameter 32 U" ACC_WIDTH $end
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$var parameter 32 V" DATA_WIDTH $end
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$var parameter 64 W" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[8] $end
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$var parameter 5 X" i $end
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$scope module u_mac $end
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$var wire 32 Y" acc_in [31:0] $end
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$var wire 8 Z" w [7:0] $end
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$var wire 8 [" x [7:0] $end
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$var wire 32 \" product_ext [31:0] $end
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$var wire 16 ]" product [15:0] $end
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$var wire 32 ^" acc_out [31:0] $end
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$var parameter 32 _" ACC_WIDTH $end
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$var parameter 32 `" DATA_WIDTH $end
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$var parameter 64 a" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[9] $end
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$var parameter 5 b" i $end
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$scope module u_mac $end
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$var wire 32 c" acc_in [31:0] $end
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$var wire 8 d" w [7:0] $end
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$var wire 8 e" x [7:0] $end
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$var wire 32 f" product_ext [31:0] $end
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$var wire 16 g" product [15:0] $end
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$var wire 32 h" acc_out [31:0] $end
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$var parameter 32 i" ACC_WIDTH $end
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$var parameter 32 j" DATA_WIDTH $end
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$var parameter 64 k" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[10] $end
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$var parameter 5 l" i $end
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$scope module u_mac $end
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$var wire 32 m" acc_in [31:0] $end
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$var wire 8 n" w [7:0] $end
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$var wire 8 o" x [7:0] $end
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$var wire 32 p" product_ext [31:0] $end
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$var wire 16 q" product [15:0] $end
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$var wire 32 r" acc_out [31:0] $end
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$var parameter 32 s" ACC_WIDTH $end
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$var parameter 32 t" DATA_WIDTH $end
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$var parameter 64 u" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[11] $end
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$var parameter 5 v" i $end
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$scope module u_mac $end
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$var wire 32 w" acc_in [31:0] $end
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$var wire 8 x" w [7:0] $end
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$var wire 8 y" x [7:0] $end
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$var wire 32 z" product_ext [31:0] $end
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$var wire 16 {" product [15:0] $end
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$var wire 32 |" acc_out [31:0] $end
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$var parameter 32 }" ACC_WIDTH $end
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$var parameter 32 ~" DATA_WIDTH $end
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$var parameter 64 !# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[12] $end
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$var parameter 5 "# i $end
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$scope module u_mac $end
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$var wire 32 ## acc_in [31:0] $end
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$var wire 8 $# w [7:0] $end
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$var wire 8 %# x [7:0] $end
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$var wire 32 &# product_ext [31:0] $end
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$var wire 16 '# product [15:0] $end
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$var wire 32 (# acc_out [31:0] $end
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$var parameter 32 )# ACC_WIDTH $end
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$var parameter 32 *# DATA_WIDTH $end
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$var parameter 64 +# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[13] $end
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$var parameter 5 ,# i $end
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$scope module u_mac $end
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$var wire 32 -# acc_in [31:0] $end
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$var wire 8 .# w [7:0] $end
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$var wire 8 /# x [7:0] $end
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$var wire 32 0# product_ext [31:0] $end
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$var wire 16 1# product [15:0] $end
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$var wire 32 2# acc_out [31:0] $end
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$var parameter 32 3# ACC_WIDTH $end
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$var parameter 32 4# DATA_WIDTH $end
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$var parameter 64 5# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[14] $end
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$var parameter 5 6# i $end
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$scope module u_mac $end
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$var wire 32 7# acc_in [31:0] $end
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$var wire 8 8# w [7:0] $end
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$var wire 8 9# x [7:0] $end
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$var wire 32 :# product_ext [31:0] $end
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$var wire 16 ;# product [15:0] $end
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$var wire 32 <# acc_out [31:0] $end
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$var parameter 32 =# ACC_WIDTH $end
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$var parameter 32 ># DATA_WIDTH $end
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$var parameter 64 ?# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[15] $end
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$var parameter 5 @# i $end
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$scope module u_mac $end
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$var wire 32 A# acc_in [31:0] $end
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$var wire 8 B# w [7:0] $end
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$var wire 8 C# x [7:0] $end
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$var wire 32 D# product_ext [31:0] $end
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$var wire 16 E# product [15:0] $end
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$var wire 32 F# acc_out [31:0] $end
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$var parameter 32 G# ACC_WIDTH $end
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$var parameter 32 H# DATA_WIDTH $end
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$var parameter 64 I# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[16] $end
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$var parameter 6 J# i $end
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$scope module u_mac $end
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$var wire 32 K# acc_in [31:0] $end
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$var wire 8 L# w [7:0] $end
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$var wire 8 M# x [7:0] $end
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$var wire 32 N# product_ext [31:0] $end
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$var wire 16 O# product [15:0] $end
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$var wire 32 P# acc_out [31:0] $end
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$var parameter 32 Q# ACC_WIDTH $end
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$var parameter 32 R# DATA_WIDTH $end
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$var parameter 64 S# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[17] $end
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$var parameter 6 T# i $end
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$scope module u_mac $end
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$var wire 32 U# acc_in [31:0] $end
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$var wire 8 V# w [7:0] $end
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$var wire 8 W# x [7:0] $end
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$var wire 32 X# product_ext [31:0] $end
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$var wire 16 Y# product [15:0] $end
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$var wire 32 Z# acc_out [31:0] $end
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$var parameter 32 [# ACC_WIDTH $end
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$var parameter 32 \# DATA_WIDTH $end
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$var parameter 64 ]# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[18] $end
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$var parameter 6 ^# i $end
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$scope module u_mac $end
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$var wire 32 _# acc_in [31:0] $end
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$var wire 8 `# w [7:0] $end
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$var wire 8 a# x [7:0] $end
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$var wire 32 b# product_ext [31:0] $end
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$var wire 16 c# product [15:0] $end
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$var wire 32 d# acc_out [31:0] $end
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$var parameter 32 e# ACC_WIDTH $end
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$var parameter 32 f# DATA_WIDTH $end
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$var parameter 64 g# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[19] $end
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$var parameter 6 h# i $end
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$scope module u_mac $end
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$var wire 32 i# acc_in [31:0] $end
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$var wire 8 j# w [7:0] $end
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$var wire 8 k# x [7:0] $end
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$var wire 32 l# product_ext [31:0] $end
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$var wire 16 m# product [15:0] $end
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$var wire 32 n# acc_out [31:0] $end
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$var parameter 32 o# ACC_WIDTH $end
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$var parameter 32 p# DATA_WIDTH $end
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$var parameter 64 q# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[20] $end
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$var parameter 6 r# i $end
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$scope module u_mac $end
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$var wire 32 s# acc_in [31:0] $end
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$var wire 8 t# w [7:0] $end
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$var wire 8 u# x [7:0] $end
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$var wire 32 v# product_ext [31:0] $end
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$var wire 16 w# product [15:0] $end
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$var wire 32 x# acc_out [31:0] $end
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$var parameter 32 y# ACC_WIDTH $end
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$var parameter 32 z# DATA_WIDTH $end
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$var parameter 64 {# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[21] $end
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$var parameter 6 |# i $end
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$scope module u_mac $end
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$var wire 32 }# acc_in [31:0] $end
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$var wire 8 ~# w [7:0] $end
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$var wire 8 !$ x [7:0] $end
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$var wire 32 "$ product_ext [31:0] $end
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$var wire 16 #$ product [15:0] $end
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$var wire 32 $$ acc_out [31:0] $end
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$var parameter 32 %$ ACC_WIDTH $end
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$var parameter 32 &$ DATA_WIDTH $end
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$var parameter 64 '$ PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[22] $end
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$var parameter 6 ($ i $end
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$scope module u_mac $end
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$var wire 32 )$ acc_in [31:0] $end
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$var wire 8 *$ w [7:0] $end
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$var wire 8 +$ x [7:0] $end
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$var wire 32 ,$ product_ext [31:0] $end
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$var wire 16 -$ product [15:0] $end
|
|
$var wire 32 .$ acc_out [31:0] $end
|
|
$var parameter 32 /$ ACC_WIDTH $end
|
|
$var parameter 32 0$ DATA_WIDTH $end
|
|
$var parameter 64 1$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[23] $end
|
|
$var parameter 6 2$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 3$ acc_in [31:0] $end
|
|
$var wire 8 4$ w [7:0] $end
|
|
$var wire 8 5$ x [7:0] $end
|
|
$var wire 32 6$ product_ext [31:0] $end
|
|
$var wire 16 7$ product [15:0] $end
|
|
$var wire 32 8$ acc_out [31:0] $end
|
|
$var parameter 32 9$ ACC_WIDTH $end
|
|
$var parameter 32 :$ DATA_WIDTH $end
|
|
$var parameter 64 ;$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[24] $end
|
|
$var parameter 6 <$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =$ acc_in [31:0] $end
|
|
$var wire 8 >$ w [7:0] $end
|
|
$var wire 8 ?$ x [7:0] $end
|
|
$var wire 32 @$ product_ext [31:0] $end
|
|
$var wire 16 A$ product [15:0] $end
|
|
$var wire 32 B$ acc_out [31:0] $end
|
|
$var parameter 32 C$ ACC_WIDTH $end
|
|
$var parameter 32 D$ DATA_WIDTH $end
|
|
$var parameter 64 E$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[25] $end
|
|
$var parameter 6 F$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G$ acc_in [31:0] $end
|
|
$var wire 8 H$ w [7:0] $end
|
|
$var wire 8 I$ x [7:0] $end
|
|
$var wire 32 J$ product_ext [31:0] $end
|
|
$var wire 16 K$ product [15:0] $end
|
|
$var wire 32 L$ acc_out [31:0] $end
|
|
$var parameter 32 M$ ACC_WIDTH $end
|
|
$var parameter 32 N$ DATA_WIDTH $end
|
|
$var parameter 64 O$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[26] $end
|
|
$var parameter 6 P$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q$ acc_in [31:0] $end
|
|
$var wire 8 R$ w [7:0] $end
|
|
$var wire 8 S$ x [7:0] $end
|
|
$var wire 32 T$ product_ext [31:0] $end
|
|
$var wire 16 U$ product [15:0] $end
|
|
$var wire 32 V$ acc_out [31:0] $end
|
|
$var parameter 32 W$ ACC_WIDTH $end
|
|
$var parameter 32 X$ DATA_WIDTH $end
|
|
$var parameter 64 Y$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[27] $end
|
|
$var parameter 6 Z$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [$ acc_in [31:0] $end
|
|
$var wire 8 \$ w [7:0] $end
|
|
$var wire 8 ]$ x [7:0] $end
|
|
$var wire 32 ^$ product_ext [31:0] $end
|
|
$var wire 16 _$ product [15:0] $end
|
|
$var wire 32 `$ acc_out [31:0] $end
|
|
$var parameter 32 a$ ACC_WIDTH $end
|
|
$var parameter 32 b$ DATA_WIDTH $end
|
|
$var parameter 64 c$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[28] $end
|
|
$var parameter 6 d$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e$ acc_in [31:0] $end
|
|
$var wire 8 f$ w [7:0] $end
|
|
$var wire 8 g$ x [7:0] $end
|
|
$var wire 32 h$ product_ext [31:0] $end
|
|
$var wire 16 i$ product [15:0] $end
|
|
$var wire 32 j$ acc_out [31:0] $end
|
|
$var parameter 32 k$ ACC_WIDTH $end
|
|
$var parameter 32 l$ DATA_WIDTH $end
|
|
$var parameter 64 m$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[29] $end
|
|
$var parameter 6 n$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o$ acc_in [31:0] $end
|
|
$var wire 8 p$ w [7:0] $end
|
|
$var wire 8 q$ x [7:0] $end
|
|
$var wire 32 r$ product_ext [31:0] $end
|
|
$var wire 16 s$ product [15:0] $end
|
|
$var wire 32 t$ acc_out [31:0] $end
|
|
$var parameter 32 u$ ACC_WIDTH $end
|
|
$var parameter 32 v$ DATA_WIDTH $end
|
|
$var parameter 64 w$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[30] $end
|
|
$var parameter 6 x$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y$ acc_in [31:0] $end
|
|
$var wire 8 z$ w [7:0] $end
|
|
$var wire 8 {$ x [7:0] $end
|
|
$var wire 32 |$ product_ext [31:0] $end
|
|
$var wire 16 }$ product [15:0] $end
|
|
$var wire 32 ~$ acc_out [31:0] $end
|
|
$var parameter 32 !% ACC_WIDTH $end
|
|
$var parameter 32 "% DATA_WIDTH $end
|
|
$var parameter 64 #% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[31] $end
|
|
$var parameter 6 $% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %% acc_in [31:0] $end
|
|
$var wire 8 &% w [7:0] $end
|
|
$var wire 8 '% x [7:0] $end
|
|
$var wire 32 (% product_ext [31:0] $end
|
|
$var wire 16 )% product [15:0] $end
|
|
$var wire 32 *% acc_out [31:0] $end
|
|
$var parameter 32 +% ACC_WIDTH $end
|
|
$var parameter 32 ,% DATA_WIDTH $end
|
|
$var parameter 64 -% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 .% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 /% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 0% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 1% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 2% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 3% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 4% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 5% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 6% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 7% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 8% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 9% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 :% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 ;% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 <% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 =% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[16] $end
|
|
$var parameter 6 >% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[17] $end
|
|
$var parameter 6 ?% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[18] $end
|
|
$var parameter 6 @% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[19] $end
|
|
$var parameter 6 A% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[20] $end
|
|
$var parameter 6 B% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[21] $end
|
|
$var parameter 6 C% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[22] $end
|
|
$var parameter 6 D% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[23] $end
|
|
$var parameter 6 E% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[24] $end
|
|
$var parameter 6 F% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[25] $end
|
|
$var parameter 6 G% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[26] $end
|
|
$var parameter 6 H% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[27] $end
|
|
$var parameter 6 I% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[28] $end
|
|
$var parameter 6 J% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[29] $end
|
|
$var parameter 6 K% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[30] $end
|
|
$var parameter 6 L% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[31] $end
|
|
$var parameter 6 M% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 N% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 O% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 P% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 Q% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 R% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 S% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 T% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 U% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 V% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[8] $end
|
|
$var parameter 5 W% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[9] $end
|
|
$var parameter 5 X% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[10] $end
|
|
$var parameter 5 Y% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[11] $end
|
|
$var parameter 5 Z% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[12] $end
|
|
$var parameter 5 [% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[13] $end
|
|
$var parameter 5 \% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[14] $end
|
|
$var parameter 5 ]% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[15] $end
|
|
$var parameter 5 ^% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 _% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 `% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 a% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 b% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 c% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 d% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 e% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 f% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 g% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 h% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 i% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 j% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 k% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 l% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 m% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 n% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 o% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[4] $end
|
|
$var parameter 4 p% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 q% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[1] $end
|
|
$var parameter 2 r% n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 s% activation [1:0] $end
|
|
$var wire 8 t% bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 u% final_acc_in_range $end
|
|
$var wire 1 v% final_acc_le_zero $end
|
|
$var wire 1 w% final_acc_upper_all0 $end
|
|
$var wire 16 x% n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 2048 y% w_bus [2047:0] $end
|
|
$var wire 2048 z% x_bus [2047:0] $end
|
|
$var wire 8 {% y_relu [7:0] $end
|
|
$var wire 8 |% y_none [7:0] $end
|
|
$var wire 256 }% x_group [255:0] $end
|
|
$var wire 256 ~% w_group [255:0] $end
|
|
$var wire 16 !& groups_real [15:0] $end
|
|
$var wire 1 "& final_acc_upper_all1 $end
|
|
$var wire 1 #& final_acc_sign $end
|
|
$var wire 32 $& final_acc [31:0] $end
|
|
$var wire 32 %& bias_ext [31:0] $end
|
|
$var wire 32 && acc_next [31:0] $end
|
|
$var parameter 32 '& ACC_WIDTH $end
|
|
$var parameter 2 (& ACT_NONE $end
|
|
$var parameter 2 )& ACT_RELU $end
|
|
$var parameter 32 *& DATA_WIDTH $end
|
|
$var parameter 32 +& GROUPS $end
|
|
$var parameter 32 ,& GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 -& N_INPUTS $end
|
|
$var parameter 32 .& PARALLEL $end
|
|
$var reg 32 /& acc [31:0] $end
|
|
$var reg 1 0& busy $end
|
|
$var reg 1 1& done $end
|
|
$var reg 1 2& finishing $end
|
|
$var reg 3 3& group_index [2:0] $end
|
|
$var reg 8 4& y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 5& acc_in [31:0] $end
|
|
$var wire 256 6& w_bus [255:0] $end
|
|
$var wire 256 7& x_bus [255:0] $end
|
|
$var wire 32 8& acc_out [31:0] $end
|
|
$var parameter 32 9& ACC_WIDTH $end
|
|
$var parameter 32 :& DATA_WIDTH $end
|
|
$var parameter 32 ;& PARALLEL $end
|
|
$var parameter 32 <& TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 =& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 >& acc_in [31:0] $end
|
|
$var wire 8 ?& w [7:0] $end
|
|
$var wire 8 @& x [7:0] $end
|
|
$var wire 32 A& product_ext [31:0] $end
|
|
$var wire 16 B& product [15:0] $end
|
|
$var wire 32 C& acc_out [31:0] $end
|
|
$var parameter 32 D& ACC_WIDTH $end
|
|
$var parameter 32 E& DATA_WIDTH $end
|
|
$var parameter 64 F& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 G& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 H& acc_in [31:0] $end
|
|
$var wire 8 I& w [7:0] $end
|
|
$var wire 8 J& x [7:0] $end
|
|
$var wire 32 K& product_ext [31:0] $end
|
|
$var wire 16 L& product [15:0] $end
|
|
$var wire 32 M& acc_out [31:0] $end
|
|
$var parameter 32 N& ACC_WIDTH $end
|
|
$var parameter 32 O& DATA_WIDTH $end
|
|
$var parameter 64 P& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 Q& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 R& acc_in [31:0] $end
|
|
$var wire 8 S& w [7:0] $end
|
|
$var wire 8 T& x [7:0] $end
|
|
$var wire 32 U& product_ext [31:0] $end
|
|
$var wire 16 V& product [15:0] $end
|
|
$var wire 32 W& acc_out [31:0] $end
|
|
$var parameter 32 X& ACC_WIDTH $end
|
|
$var parameter 32 Y& DATA_WIDTH $end
|
|
$var parameter 64 Z& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 [& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 \& acc_in [31:0] $end
|
|
$var wire 8 ]& w [7:0] $end
|
|
$var wire 8 ^& x [7:0] $end
|
|
$var wire 32 _& product_ext [31:0] $end
|
|
$var wire 16 `& product [15:0] $end
|
|
$var wire 32 a& acc_out [31:0] $end
|
|
$var parameter 32 b& ACC_WIDTH $end
|
|
$var parameter 32 c& DATA_WIDTH $end
|
|
$var parameter 64 d& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 e& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 f& acc_in [31:0] $end
|
|
$var wire 8 g& w [7:0] $end
|
|
$var wire 8 h& x [7:0] $end
|
|
$var wire 32 i& product_ext [31:0] $end
|
|
$var wire 16 j& product [15:0] $end
|
|
$var wire 32 k& acc_out [31:0] $end
|
|
$var parameter 32 l& ACC_WIDTH $end
|
|
$var parameter 32 m& DATA_WIDTH $end
|
|
$var parameter 64 n& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 o& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 p& acc_in [31:0] $end
|
|
$var wire 8 q& w [7:0] $end
|
|
$var wire 8 r& x [7:0] $end
|
|
$var wire 32 s& product_ext [31:0] $end
|
|
$var wire 16 t& product [15:0] $end
|
|
$var wire 32 u& acc_out [31:0] $end
|
|
$var parameter 32 v& ACC_WIDTH $end
|
|
$var parameter 32 w& DATA_WIDTH $end
|
|
$var parameter 64 x& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 y& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 z& acc_in [31:0] $end
|
|
$var wire 8 {& w [7:0] $end
|
|
$var wire 8 |& x [7:0] $end
|
|
$var wire 32 }& product_ext [31:0] $end
|
|
$var wire 16 ~& product [15:0] $end
|
|
$var wire 32 !' acc_out [31:0] $end
|
|
$var parameter 32 "' ACC_WIDTH $end
|
|
$var parameter 32 #' DATA_WIDTH $end
|
|
$var parameter 64 $' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 %' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 &' acc_in [31:0] $end
|
|
$var wire 8 '' w [7:0] $end
|
|
$var wire 8 (' x [7:0] $end
|
|
$var wire 32 )' product_ext [31:0] $end
|
|
$var wire 16 *' product [15:0] $end
|
|
$var wire 32 +' acc_out [31:0] $end
|
|
$var parameter 32 ,' ACC_WIDTH $end
|
|
$var parameter 32 -' DATA_WIDTH $end
|
|
$var parameter 64 .' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 /' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 0' acc_in [31:0] $end
|
|
$var wire 8 1' w [7:0] $end
|
|
$var wire 8 2' x [7:0] $end
|
|
$var wire 32 3' product_ext [31:0] $end
|
|
$var wire 16 4' product [15:0] $end
|
|
$var wire 32 5' acc_out [31:0] $end
|
|
$var parameter 32 6' ACC_WIDTH $end
|
|
$var parameter 32 7' DATA_WIDTH $end
|
|
$var parameter 64 8' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 9' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 :' acc_in [31:0] $end
|
|
$var wire 8 ;' w [7:0] $end
|
|
$var wire 8 <' x [7:0] $end
|
|
$var wire 32 =' product_ext [31:0] $end
|
|
$var wire 16 >' product [15:0] $end
|
|
$var wire 32 ?' acc_out [31:0] $end
|
|
$var parameter 32 @' ACC_WIDTH $end
|
|
$var parameter 32 A' DATA_WIDTH $end
|
|
$var parameter 64 B' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 C' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 D' acc_in [31:0] $end
|
|
$var wire 8 E' w [7:0] $end
|
|
$var wire 8 F' x [7:0] $end
|
|
$var wire 32 G' product_ext [31:0] $end
|
|
$var wire 16 H' product [15:0] $end
|
|
$var wire 32 I' acc_out [31:0] $end
|
|
$var parameter 32 J' ACC_WIDTH $end
|
|
$var parameter 32 K' DATA_WIDTH $end
|
|
$var parameter 64 L' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 M' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 N' acc_in [31:0] $end
|
|
$var wire 8 O' w [7:0] $end
|
|
$var wire 8 P' x [7:0] $end
|
|
$var wire 32 Q' product_ext [31:0] $end
|
|
$var wire 16 R' product [15:0] $end
|
|
$var wire 32 S' acc_out [31:0] $end
|
|
$var parameter 32 T' ACC_WIDTH $end
|
|
$var parameter 32 U' DATA_WIDTH $end
|
|
$var parameter 64 V' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 W' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 X' acc_in [31:0] $end
|
|
$var wire 8 Y' w [7:0] $end
|
|
$var wire 8 Z' x [7:0] $end
|
|
$var wire 32 [' product_ext [31:0] $end
|
|
$var wire 16 \' product [15:0] $end
|
|
$var wire 32 ]' acc_out [31:0] $end
|
|
$var parameter 32 ^' ACC_WIDTH $end
|
|
$var parameter 32 _' DATA_WIDTH $end
|
|
$var parameter 64 `' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 a' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 b' acc_in [31:0] $end
|
|
$var wire 8 c' w [7:0] $end
|
|
$var wire 8 d' x [7:0] $end
|
|
$var wire 32 e' product_ext [31:0] $end
|
|
$var wire 16 f' product [15:0] $end
|
|
$var wire 32 g' acc_out [31:0] $end
|
|
$var parameter 32 h' ACC_WIDTH $end
|
|
$var parameter 32 i' DATA_WIDTH $end
|
|
$var parameter 64 j' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 k' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 l' acc_in [31:0] $end
|
|
$var wire 8 m' w [7:0] $end
|
|
$var wire 8 n' x [7:0] $end
|
|
$var wire 32 o' product_ext [31:0] $end
|
|
$var wire 16 p' product [15:0] $end
|
|
$var wire 32 q' acc_out [31:0] $end
|
|
$var parameter 32 r' ACC_WIDTH $end
|
|
$var parameter 32 s' DATA_WIDTH $end
|
|
$var parameter 64 t' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 u' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 v' acc_in [31:0] $end
|
|
$var wire 8 w' w [7:0] $end
|
|
$var wire 8 x' x [7:0] $end
|
|
$var wire 32 y' product_ext [31:0] $end
|
|
$var wire 16 z' product [15:0] $end
|
|
$var wire 32 {' acc_out [31:0] $end
|
|
$var parameter 32 |' ACC_WIDTH $end
|
|
$var parameter 32 }' DATA_WIDTH $end
|
|
$var parameter 64 ~' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[16] $end
|
|
$var parameter 6 !( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 "( acc_in [31:0] $end
|
|
$var wire 8 #( w [7:0] $end
|
|
$var wire 8 $( x [7:0] $end
|
|
$var wire 32 %( product_ext [31:0] $end
|
|
$var wire 16 &( product [15:0] $end
|
|
$var wire 32 '( acc_out [31:0] $end
|
|
$var parameter 32 (( ACC_WIDTH $end
|
|
$var parameter 32 )( DATA_WIDTH $end
|
|
$var parameter 64 *( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[17] $end
|
|
$var parameter 6 +( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ,( acc_in [31:0] $end
|
|
$var wire 8 -( w [7:0] $end
|
|
$var wire 8 .( x [7:0] $end
|
|
$var wire 32 /( product_ext [31:0] $end
|
|
$var wire 16 0( product [15:0] $end
|
|
$var wire 32 1( acc_out [31:0] $end
|
|
$var parameter 32 2( ACC_WIDTH $end
|
|
$var parameter 32 3( DATA_WIDTH $end
|
|
$var parameter 64 4( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[18] $end
|
|
$var parameter 6 5( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 6( acc_in [31:0] $end
|
|
$var wire 8 7( w [7:0] $end
|
|
$var wire 8 8( x [7:0] $end
|
|
$var wire 32 9( product_ext [31:0] $end
|
|
$var wire 16 :( product [15:0] $end
|
|
$var wire 32 ;( acc_out [31:0] $end
|
|
$var parameter 32 <( ACC_WIDTH $end
|
|
$var parameter 32 =( DATA_WIDTH $end
|
|
$var parameter 64 >( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[19] $end
|
|
$var parameter 6 ?( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 @( acc_in [31:0] $end
|
|
$var wire 8 A( w [7:0] $end
|
|
$var wire 8 B( x [7:0] $end
|
|
$var wire 32 C( product_ext [31:0] $end
|
|
$var wire 16 D( product [15:0] $end
|
|
$var wire 32 E( acc_out [31:0] $end
|
|
$var parameter 32 F( ACC_WIDTH $end
|
|
$var parameter 32 G( DATA_WIDTH $end
|
|
$var parameter 64 H( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[20] $end
|
|
$var parameter 6 I( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 J( acc_in [31:0] $end
|
|
$var wire 8 K( w [7:0] $end
|
|
$var wire 8 L( x [7:0] $end
|
|
$var wire 32 M( product_ext [31:0] $end
|
|
$var wire 16 N( product [15:0] $end
|
|
$var wire 32 O( acc_out [31:0] $end
|
|
$var parameter 32 P( ACC_WIDTH $end
|
|
$var parameter 32 Q( DATA_WIDTH $end
|
|
$var parameter 64 R( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[21] $end
|
|
$var parameter 6 S( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 T( acc_in [31:0] $end
|
|
$var wire 8 U( w [7:0] $end
|
|
$var wire 8 V( x [7:0] $end
|
|
$var wire 32 W( product_ext [31:0] $end
|
|
$var wire 16 X( product [15:0] $end
|
|
$var wire 32 Y( acc_out [31:0] $end
|
|
$var parameter 32 Z( ACC_WIDTH $end
|
|
$var parameter 32 [( DATA_WIDTH $end
|
|
$var parameter 64 \( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[22] $end
|
|
$var parameter 6 ]( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ^( acc_in [31:0] $end
|
|
$var wire 8 _( w [7:0] $end
|
|
$var wire 8 `( x [7:0] $end
|
|
$var wire 32 a( product_ext [31:0] $end
|
|
$var wire 16 b( product [15:0] $end
|
|
$var wire 32 c( acc_out [31:0] $end
|
|
$var parameter 32 d( ACC_WIDTH $end
|
|
$var parameter 32 e( DATA_WIDTH $end
|
|
$var parameter 64 f( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[23] $end
|
|
$var parameter 6 g( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 h( acc_in [31:0] $end
|
|
$var wire 8 i( w [7:0] $end
|
|
$var wire 8 j( x [7:0] $end
|
|
$var wire 32 k( product_ext [31:0] $end
|
|
$var wire 16 l( product [15:0] $end
|
|
$var wire 32 m( acc_out [31:0] $end
|
|
$var parameter 32 n( ACC_WIDTH $end
|
|
$var parameter 32 o( DATA_WIDTH $end
|
|
$var parameter 64 p( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[24] $end
|
|
$var parameter 6 q( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 r( acc_in [31:0] $end
|
|
$var wire 8 s( w [7:0] $end
|
|
$var wire 8 t( x [7:0] $end
|
|
$var wire 32 u( product_ext [31:0] $end
|
|
$var wire 16 v( product [15:0] $end
|
|
$var wire 32 w( acc_out [31:0] $end
|
|
$var parameter 32 x( ACC_WIDTH $end
|
|
$var parameter 32 y( DATA_WIDTH $end
|
|
$var parameter 64 z( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[25] $end
|
|
$var parameter 6 {( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 |( acc_in [31:0] $end
|
|
$var wire 8 }( w [7:0] $end
|
|
$var wire 8 ~( x [7:0] $end
|
|
$var wire 32 !) product_ext [31:0] $end
|
|
$var wire 16 ") product [15:0] $end
|
|
$var wire 32 #) acc_out [31:0] $end
|
|
$var parameter 32 $) ACC_WIDTH $end
|
|
$var parameter 32 %) DATA_WIDTH $end
|
|
$var parameter 64 &) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[26] $end
|
|
$var parameter 6 ') i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 () acc_in [31:0] $end
|
|
$var wire 8 )) w [7:0] $end
|
|
$var wire 8 *) x [7:0] $end
|
|
$var wire 32 +) product_ext [31:0] $end
|
|
$var wire 16 ,) product [15:0] $end
|
|
$var wire 32 -) acc_out [31:0] $end
|
|
$var parameter 32 .) ACC_WIDTH $end
|
|
$var parameter 32 /) DATA_WIDTH $end
|
|
$var parameter 64 0) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[27] $end
|
|
$var parameter 6 1) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 2) acc_in [31:0] $end
|
|
$var wire 8 3) w [7:0] $end
|
|
$var wire 8 4) x [7:0] $end
|
|
$var wire 32 5) product_ext [31:0] $end
|
|
$var wire 16 6) product [15:0] $end
|
|
$var wire 32 7) acc_out [31:0] $end
|
|
$var parameter 32 8) ACC_WIDTH $end
|
|
$var parameter 32 9) DATA_WIDTH $end
|
|
$var parameter 64 :) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[28] $end
|
|
$var parameter 6 ;) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 <) acc_in [31:0] $end
|
|
$var wire 8 =) w [7:0] $end
|
|
$var wire 8 >) x [7:0] $end
|
|
$var wire 32 ?) product_ext [31:0] $end
|
|
$var wire 16 @) product [15:0] $end
|
|
$var wire 32 A) acc_out [31:0] $end
|
|
$var parameter 32 B) ACC_WIDTH $end
|
|
$var parameter 32 C) DATA_WIDTH $end
|
|
$var parameter 64 D) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[29] $end
|
|
$var parameter 6 E) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 F) acc_in [31:0] $end
|
|
$var wire 8 G) w [7:0] $end
|
|
$var wire 8 H) x [7:0] $end
|
|
$var wire 32 I) product_ext [31:0] $end
|
|
$var wire 16 J) product [15:0] $end
|
|
$var wire 32 K) acc_out [31:0] $end
|
|
$var parameter 32 L) ACC_WIDTH $end
|
|
$var parameter 32 M) DATA_WIDTH $end
|
|
$var parameter 64 N) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[30] $end
|
|
$var parameter 6 O) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 P) acc_in [31:0] $end
|
|
$var wire 8 Q) w [7:0] $end
|
|
$var wire 8 R) x [7:0] $end
|
|
$var wire 32 S) product_ext [31:0] $end
|
|
$var wire 16 T) product [15:0] $end
|
|
$var wire 32 U) acc_out [31:0] $end
|
|
$var parameter 32 V) ACC_WIDTH $end
|
|
$var parameter 32 W) DATA_WIDTH $end
|
|
$var parameter 64 X) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[31] $end
|
|
$var parameter 6 Y) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Z) acc_in [31:0] $end
|
|
$var wire 8 [) w [7:0] $end
|
|
$var wire 8 \) x [7:0] $end
|
|
$var wire 32 ]) product_ext [31:0] $end
|
|
$var wire 16 ^) product [15:0] $end
|
|
$var wire 32 _) acc_out [31:0] $end
|
|
$var parameter 32 `) ACC_WIDTH $end
|
|
$var parameter 32 a) DATA_WIDTH $end
|
|
$var parameter 64 b) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 c) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 d) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 e) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 f) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 g) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 h) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 i) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 j) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 k) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 l) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 m) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 n) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 o) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 p) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 q) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 r) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[16] $end
|
|
$var parameter 6 s) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[17] $end
|
|
$var parameter 6 t) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[18] $end
|
|
$var parameter 6 u) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[19] $end
|
|
$var parameter 6 v) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[20] $end
|
|
$var parameter 6 w) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[21] $end
|
|
$var parameter 6 x) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[22] $end
|
|
$var parameter 6 y) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[23] $end
|
|
$var parameter 6 z) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[24] $end
|
|
$var parameter 6 {) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[25] $end
|
|
$var parameter 6 |) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[26] $end
|
|
$var parameter 6 }) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[27] $end
|
|
$var parameter 6 ~) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[28] $end
|
|
$var parameter 6 !* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[29] $end
|
|
$var parameter 6 "* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[30] $end
|
|
$var parameter 6 #* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[31] $end
|
|
$var parameter 6 $* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 %* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 &* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 '* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 (* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 )* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 ** node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 +* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 ,* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 -* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[8] $end
|
|
$var parameter 5 .* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[9] $end
|
|
$var parameter 5 /* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[10] $end
|
|
$var parameter 5 0* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[11] $end
|
|
$var parameter 5 1* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[12] $end
|
|
$var parameter 5 2* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[13] $end
|
|
$var parameter 5 3* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[14] $end
|
|
$var parameter 5 4* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[15] $end
|
|
$var parameter 5 5* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 6* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 7* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 8* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 9* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 :* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 ;* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 <* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 =* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 >* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 ?* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 @* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 A* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 B* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 C* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 D* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 E* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 F* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[4] $end
|
|
$var parameter 4 G* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 H* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[2] $end
|
|
$var parameter 3 I* n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 J* activation [1:0] $end
|
|
$var wire 8 K* bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 L* final_acc_in_range $end
|
|
$var wire 1 M* final_acc_le_zero $end
|
|
$var wire 1 N* final_acc_upper_all0 $end
|
|
$var wire 16 O* n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 2048 P* w_bus [2047:0] $end
|
|
$var wire 2048 Q* x_bus [2047:0] $end
|
|
$var wire 8 R* y_relu [7:0] $end
|
|
$var wire 8 S* y_none [7:0] $end
|
|
$var wire 256 T* x_group [255:0] $end
|
|
$var wire 256 U* w_group [255:0] $end
|
|
$var wire 16 V* groups_real [15:0] $end
|
|
$var wire 1 W* final_acc_upper_all1 $end
|
|
$var wire 1 X* final_acc_sign $end
|
|
$var wire 32 Y* final_acc [31:0] $end
|
|
$var wire 32 Z* bias_ext [31:0] $end
|
|
$var wire 32 [* acc_next [31:0] $end
|
|
$var parameter 32 \* ACC_WIDTH $end
|
|
$var parameter 2 ]* ACT_NONE $end
|
|
$var parameter 2 ^* ACT_RELU $end
|
|
$var parameter 32 _* DATA_WIDTH $end
|
|
$var parameter 32 `* GROUPS $end
|
|
$var parameter 32 a* GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 b* N_INPUTS $end
|
|
$var parameter 32 c* PARALLEL $end
|
|
$var reg 32 d* acc [31:0] $end
|
|
$var reg 1 e* busy $end
|
|
$var reg 1 f* done $end
|
|
$var reg 1 g* finishing $end
|
|
$var reg 3 h* group_index [2:0] $end
|
|
$var reg 8 i* y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 j* acc_in [31:0] $end
|
|
$var wire 256 k* w_bus [255:0] $end
|
|
$var wire 256 l* x_bus [255:0] $end
|
|
$var wire 32 m* acc_out [31:0] $end
|
|
$var parameter 32 n* ACC_WIDTH $end
|
|
$var parameter 32 o* DATA_WIDTH $end
|
|
$var parameter 32 p* PARALLEL $end
|
|
$var parameter 32 q* TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 r* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 s* acc_in [31:0] $end
|
|
$var wire 8 t* w [7:0] $end
|
|
$var wire 8 u* x [7:0] $end
|
|
$var wire 32 v* product_ext [31:0] $end
|
|
$var wire 16 w* product [15:0] $end
|
|
$var wire 32 x* acc_out [31:0] $end
|
|
$var parameter 32 y* ACC_WIDTH $end
|
|
$var parameter 32 z* DATA_WIDTH $end
|
|
$var parameter 64 {* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 |* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 }* acc_in [31:0] $end
|
|
$var wire 8 ~* w [7:0] $end
|
|
$var wire 8 !+ x [7:0] $end
|
|
$var wire 32 "+ product_ext [31:0] $end
|
|
$var wire 16 #+ product [15:0] $end
|
|
$var wire 32 $+ acc_out [31:0] $end
|
|
$var parameter 32 %+ ACC_WIDTH $end
|
|
$var parameter 32 &+ DATA_WIDTH $end
|
|
$var parameter 64 '+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 (+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 )+ acc_in [31:0] $end
|
|
$var wire 8 *+ w [7:0] $end
|
|
$var wire 8 ++ x [7:0] $end
|
|
$var wire 32 ,+ product_ext [31:0] $end
|
|
$var wire 16 -+ product [15:0] $end
|
|
$var wire 32 .+ acc_out [31:0] $end
|
|
$var parameter 32 /+ ACC_WIDTH $end
|
|
$var parameter 32 0+ DATA_WIDTH $end
|
|
$var parameter 64 1+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 2+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 3+ acc_in [31:0] $end
|
|
$var wire 8 4+ w [7:0] $end
|
|
$var wire 8 5+ x [7:0] $end
|
|
$var wire 32 6+ product_ext [31:0] $end
|
|
$var wire 16 7+ product [15:0] $end
|
|
$var wire 32 8+ acc_out [31:0] $end
|
|
$var parameter 32 9+ ACC_WIDTH $end
|
|
$var parameter 32 :+ DATA_WIDTH $end
|
|
$var parameter 64 ;+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 <+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =+ acc_in [31:0] $end
|
|
$var wire 8 >+ w [7:0] $end
|
|
$var wire 8 ?+ x [7:0] $end
|
|
$var wire 32 @+ product_ext [31:0] $end
|
|
$var wire 16 A+ product [15:0] $end
|
|
$var wire 32 B+ acc_out [31:0] $end
|
|
$var parameter 32 C+ ACC_WIDTH $end
|
|
$var parameter 32 D+ DATA_WIDTH $end
|
|
$var parameter 64 E+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 F+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G+ acc_in [31:0] $end
|
|
$var wire 8 H+ w [7:0] $end
|
|
$var wire 8 I+ x [7:0] $end
|
|
$var wire 32 J+ product_ext [31:0] $end
|
|
$var wire 16 K+ product [15:0] $end
|
|
$var wire 32 L+ acc_out [31:0] $end
|
|
$var parameter 32 M+ ACC_WIDTH $end
|
|
$var parameter 32 N+ DATA_WIDTH $end
|
|
$var parameter 64 O+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 P+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q+ acc_in [31:0] $end
|
|
$var wire 8 R+ w [7:0] $end
|
|
$var wire 8 S+ x [7:0] $end
|
|
$var wire 32 T+ product_ext [31:0] $end
|
|
$var wire 16 U+ product [15:0] $end
|
|
$var wire 32 V+ acc_out [31:0] $end
|
|
$var parameter 32 W+ ACC_WIDTH $end
|
|
$var parameter 32 X+ DATA_WIDTH $end
|
|
$var parameter 64 Y+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 Z+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [+ acc_in [31:0] $end
|
|
$var wire 8 \+ w [7:0] $end
|
|
$var wire 8 ]+ x [7:0] $end
|
|
$var wire 32 ^+ product_ext [31:0] $end
|
|
$var wire 16 _+ product [15:0] $end
|
|
$var wire 32 `+ acc_out [31:0] $end
|
|
$var parameter 32 a+ ACC_WIDTH $end
|
|
$var parameter 32 b+ DATA_WIDTH $end
|
|
$var parameter 64 c+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 d+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e+ acc_in [31:0] $end
|
|
$var wire 8 f+ w [7:0] $end
|
|
$var wire 8 g+ x [7:0] $end
|
|
$var wire 32 h+ product_ext [31:0] $end
|
|
$var wire 16 i+ product [15:0] $end
|
|
$var wire 32 j+ acc_out [31:0] $end
|
|
$var parameter 32 k+ ACC_WIDTH $end
|
|
$var parameter 32 l+ DATA_WIDTH $end
|
|
$var parameter 64 m+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 n+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o+ acc_in [31:0] $end
|
|
$var wire 8 p+ w [7:0] $end
|
|
$var wire 8 q+ x [7:0] $end
|
|
$var wire 32 r+ product_ext [31:0] $end
|
|
$var wire 16 s+ product [15:0] $end
|
|
$var wire 32 t+ acc_out [31:0] $end
|
|
$var parameter 32 u+ ACC_WIDTH $end
|
|
$var parameter 32 v+ DATA_WIDTH $end
|
|
$var parameter 64 w+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 x+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y+ acc_in [31:0] $end
|
|
$var wire 8 z+ w [7:0] $end
|
|
$var wire 8 {+ x [7:0] $end
|
|
$var wire 32 |+ product_ext [31:0] $end
|
|
$var wire 16 }+ product [15:0] $end
|
|
$var wire 32 ~+ acc_out [31:0] $end
|
|
$var parameter 32 !, ACC_WIDTH $end
|
|
$var parameter 32 ", DATA_WIDTH $end
|
|
$var parameter 64 #, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 $, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %, acc_in [31:0] $end
|
|
$var wire 8 &, w [7:0] $end
|
|
$var wire 8 ', x [7:0] $end
|
|
$var wire 32 (, product_ext [31:0] $end
|
|
$var wire 16 ), product [15:0] $end
|
|
$var wire 32 *, acc_out [31:0] $end
|
|
$var parameter 32 +, ACC_WIDTH $end
|
|
$var parameter 32 ,, DATA_WIDTH $end
|
|
$var parameter 64 -, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 ., i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 /, acc_in [31:0] $end
|
|
$var wire 8 0, w [7:0] $end
|
|
$var wire 8 1, x [7:0] $end
|
|
$var wire 32 2, product_ext [31:0] $end
|
|
$var wire 16 3, product [15:0] $end
|
|
$var wire 32 4, acc_out [31:0] $end
|
|
$var parameter 32 5, ACC_WIDTH $end
|
|
$var parameter 32 6, DATA_WIDTH $end
|
|
$var parameter 64 7, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 8, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 9, acc_in [31:0] $end
|
|
$var wire 8 :, w [7:0] $end
|
|
$var wire 8 ;, x [7:0] $end
|
|
$var wire 32 <, product_ext [31:0] $end
|
|
$var wire 16 =, product [15:0] $end
|
|
$var wire 32 >, acc_out [31:0] $end
|
|
$var parameter 32 ?, ACC_WIDTH $end
|
|
$var parameter 32 @, DATA_WIDTH $end
|
|
$var parameter 64 A, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 B, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 C, acc_in [31:0] $end
|
|
$var wire 8 D, w [7:0] $end
|
|
$var wire 8 E, x [7:0] $end
|
|
$var wire 32 F, product_ext [31:0] $end
|
|
$var wire 16 G, product [15:0] $end
|
|
$var wire 32 H, acc_out [31:0] $end
|
|
$var parameter 32 I, ACC_WIDTH $end
|
|
$var parameter 32 J, DATA_WIDTH $end
|
|
$var parameter 64 K, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 L, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 M, acc_in [31:0] $end
|
|
$var wire 8 N, w [7:0] $end
|
|
$var wire 8 O, x [7:0] $end
|
|
$var wire 32 P, product_ext [31:0] $end
|
|
$var wire 16 Q, product [15:0] $end
|
|
$var wire 32 R, acc_out [31:0] $end
|
|
$var parameter 32 S, ACC_WIDTH $end
|
|
$var parameter 32 T, DATA_WIDTH $end
|
|
$var parameter 64 U, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[16] $end
|
|
$var parameter 6 V, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 W, acc_in [31:0] $end
|
|
$var wire 8 X, w [7:0] $end
|
|
$var wire 8 Y, x [7:0] $end
|
|
$var wire 32 Z, product_ext [31:0] $end
|
|
$var wire 16 [, product [15:0] $end
|
|
$var wire 32 \, acc_out [31:0] $end
|
|
$var parameter 32 ], ACC_WIDTH $end
|
|
$var parameter 32 ^, DATA_WIDTH $end
|
|
$var parameter 64 _, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[17] $end
|
|
$var parameter 6 `, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 a, acc_in [31:0] $end
|
|
$var wire 8 b, w [7:0] $end
|
|
$var wire 8 c, x [7:0] $end
|
|
$var wire 32 d, product_ext [31:0] $end
|
|
$var wire 16 e, product [15:0] $end
|
|
$var wire 32 f, acc_out [31:0] $end
|
|
$var parameter 32 g, ACC_WIDTH $end
|
|
$var parameter 32 h, DATA_WIDTH $end
|
|
$var parameter 64 i, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[18] $end
|
|
$var parameter 6 j, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 k, acc_in [31:0] $end
|
|
$var wire 8 l, w [7:0] $end
|
|
$var wire 8 m, x [7:0] $end
|
|
$var wire 32 n, product_ext [31:0] $end
|
|
$var wire 16 o, product [15:0] $end
|
|
$var wire 32 p, acc_out [31:0] $end
|
|
$var parameter 32 q, ACC_WIDTH $end
|
|
$var parameter 32 r, DATA_WIDTH $end
|
|
$var parameter 64 s, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[19] $end
|
|
$var parameter 6 t, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 u, acc_in [31:0] $end
|
|
$var wire 8 v, w [7:0] $end
|
|
$var wire 8 w, x [7:0] $end
|
|
$var wire 32 x, product_ext [31:0] $end
|
|
$var wire 16 y, product [15:0] $end
|
|
$var wire 32 z, acc_out [31:0] $end
|
|
$var parameter 32 {, ACC_WIDTH $end
|
|
$var parameter 32 |, DATA_WIDTH $end
|
|
$var parameter 64 }, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[20] $end
|
|
$var parameter 6 ~, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 !- acc_in [31:0] $end
|
|
$var wire 8 "- w [7:0] $end
|
|
$var wire 8 #- x [7:0] $end
|
|
$var wire 32 $- product_ext [31:0] $end
|
|
$var wire 16 %- product [15:0] $end
|
|
$var wire 32 &- acc_out [31:0] $end
|
|
$var parameter 32 '- ACC_WIDTH $end
|
|
$var parameter 32 (- DATA_WIDTH $end
|
|
$var parameter 64 )- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[21] $end
|
|
$var parameter 6 *- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 +- acc_in [31:0] $end
|
|
$var wire 8 ,- w [7:0] $end
|
|
$var wire 8 -- x [7:0] $end
|
|
$var wire 32 .- product_ext [31:0] $end
|
|
$var wire 16 /- product [15:0] $end
|
|
$var wire 32 0- acc_out [31:0] $end
|
|
$var parameter 32 1- ACC_WIDTH $end
|
|
$var parameter 32 2- DATA_WIDTH $end
|
|
$var parameter 64 3- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[22] $end
|
|
$var parameter 6 4- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 5- acc_in [31:0] $end
|
|
$var wire 8 6- w [7:0] $end
|
|
$var wire 8 7- x [7:0] $end
|
|
$var wire 32 8- product_ext [31:0] $end
|
|
$var wire 16 9- product [15:0] $end
|
|
$var wire 32 :- acc_out [31:0] $end
|
|
$var parameter 32 ;- ACC_WIDTH $end
|
|
$var parameter 32 <- DATA_WIDTH $end
|
|
$var parameter 64 =- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[23] $end
|
|
$var parameter 6 >- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ?- acc_in [31:0] $end
|
|
$var wire 8 @- w [7:0] $end
|
|
$var wire 8 A- x [7:0] $end
|
|
$var wire 32 B- product_ext [31:0] $end
|
|
$var wire 16 C- product [15:0] $end
|
|
$var wire 32 D- acc_out [31:0] $end
|
|
$var parameter 32 E- ACC_WIDTH $end
|
|
$var parameter 32 F- DATA_WIDTH $end
|
|
$var parameter 64 G- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[24] $end
|
|
$var parameter 6 H- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 I- acc_in [31:0] $end
|
|
$var wire 8 J- w [7:0] $end
|
|
$var wire 8 K- x [7:0] $end
|
|
$var wire 32 L- product_ext [31:0] $end
|
|
$var wire 16 M- product [15:0] $end
|
|
$var wire 32 N- acc_out [31:0] $end
|
|
$var parameter 32 O- ACC_WIDTH $end
|
|
$var parameter 32 P- DATA_WIDTH $end
|
|
$var parameter 64 Q- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[25] $end
|
|
$var parameter 6 R- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 S- acc_in [31:0] $end
|
|
$var wire 8 T- w [7:0] $end
|
|
$var wire 8 U- x [7:0] $end
|
|
$var wire 32 V- product_ext [31:0] $end
|
|
$var wire 16 W- product [15:0] $end
|
|
$var wire 32 X- acc_out [31:0] $end
|
|
$var parameter 32 Y- ACC_WIDTH $end
|
|
$var parameter 32 Z- DATA_WIDTH $end
|
|
$var parameter 64 [- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[26] $end
|
|
$var parameter 6 \- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ]- acc_in [31:0] $end
|
|
$var wire 8 ^- w [7:0] $end
|
|
$var wire 8 _- x [7:0] $end
|
|
$var wire 32 `- product_ext [31:0] $end
|
|
$var wire 16 a- product [15:0] $end
|
|
$var wire 32 b- acc_out [31:0] $end
|
|
$var parameter 32 c- ACC_WIDTH $end
|
|
$var parameter 32 d- DATA_WIDTH $end
|
|
$var parameter 64 e- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[27] $end
|
|
$var parameter 6 f- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 g- acc_in [31:0] $end
|
|
$var wire 8 h- w [7:0] $end
|
|
$var wire 8 i- x [7:0] $end
|
|
$var wire 32 j- product_ext [31:0] $end
|
|
$var wire 16 k- product [15:0] $end
|
|
$var wire 32 l- acc_out [31:0] $end
|
|
$var parameter 32 m- ACC_WIDTH $end
|
|
$var parameter 32 n- DATA_WIDTH $end
|
|
$var parameter 64 o- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[28] $end
|
|
$var parameter 6 p- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 q- acc_in [31:0] $end
|
|
$var wire 8 r- w [7:0] $end
|
|
$var wire 8 s- x [7:0] $end
|
|
$var wire 32 t- product_ext [31:0] $end
|
|
$var wire 16 u- product [15:0] $end
|
|
$var wire 32 v- acc_out [31:0] $end
|
|
$var parameter 32 w- ACC_WIDTH $end
|
|
$var parameter 32 x- DATA_WIDTH $end
|
|
$var parameter 64 y- PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[29] $end
|
|
$var parameter 6 z- i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 {- acc_in [31:0] $end
|
|
$var wire 8 |- w [7:0] $end
|
|
$var wire 8 }- x [7:0] $end
|
|
$var wire 32 ~- product_ext [31:0] $end
|
|
$var wire 16 !. product [15:0] $end
|
|
$var wire 32 ". acc_out [31:0] $end
|
|
$var parameter 32 #. ACC_WIDTH $end
|
|
$var parameter 32 $. DATA_WIDTH $end
|
|
$var parameter 64 %. PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[30] $end
|
|
$var parameter 6 &. i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 '. acc_in [31:0] $end
|
|
$var wire 8 (. w [7:0] $end
|
|
$var wire 8 ). x [7:0] $end
|
|
$var wire 32 *. product_ext [31:0] $end
|
|
$var wire 16 +. product [15:0] $end
|
|
$var wire 32 ,. acc_out [31:0] $end
|
|
$var parameter 32 -. ACC_WIDTH $end
|
|
$var parameter 32 .. DATA_WIDTH $end
|
|
$var parameter 64 /. PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[31] $end
|
|
$var parameter 6 0. i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 1. acc_in [31:0] $end
|
|
$var wire 8 2. w [7:0] $end
|
|
$var wire 8 3. x [7:0] $end
|
|
$var wire 32 4. product_ext [31:0] $end
|
|
$var wire 16 5. product [15:0] $end
|
|
$var wire 32 6. acc_out [31:0] $end
|
|
$var parameter 32 7. ACC_WIDTH $end
|
|
$var parameter 32 8. DATA_WIDTH $end
|
|
$var parameter 64 9. PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 :. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 ;. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 <. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 =. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 >. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 ?. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 @. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 A. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 B. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 C. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 D. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 E. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 F. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 G. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 H. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 I. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[16] $end
|
|
$var parameter 6 J. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[17] $end
|
|
$var parameter 6 K. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[18] $end
|
|
$var parameter 6 L. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[19] $end
|
|
$var parameter 6 M. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[20] $end
|
|
$var parameter 6 N. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[21] $end
|
|
$var parameter 6 O. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[22] $end
|
|
$var parameter 6 P. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[23] $end
|
|
$var parameter 6 Q. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[24] $end
|
|
$var parameter 6 R. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[25] $end
|
|
$var parameter 6 S. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[26] $end
|
|
$var parameter 6 T. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[27] $end
|
|
$var parameter 6 U. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[28] $end
|
|
$var parameter 6 V. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[29] $end
|
|
$var parameter 6 W. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[30] $end
|
|
$var parameter 6 X. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[31] $end
|
|
$var parameter 6 Y. i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 Z. level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 [. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 \. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 ]. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 ^. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 _. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 `. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 a. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 b. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[8] $end
|
|
$var parameter 5 c. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[9] $end
|
|
$var parameter 5 d. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[10] $end
|
|
$var parameter 5 e. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[11] $end
|
|
$var parameter 5 f. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[12] $end
|
|
$var parameter 5 g. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[13] $end
|
|
$var parameter 5 h. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[14] $end
|
|
$var parameter 5 i. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[15] $end
|
|
$var parameter 5 j. node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 k. level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 l. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 m. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 n. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 o. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 p. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 q. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 r. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 s. node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 t. level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 u. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 v. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 w. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 x. node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 y. level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 z. node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 {. node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[4] $end
|
|
$var parameter 4 |. level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 }. node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[3] $end
|
|
$var parameter 3 ~. n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 !/ activation [1:0] $end
|
|
$var wire 8 "/ bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 #/ final_acc_in_range $end
|
|
$var wire 1 $/ final_acc_le_zero $end
|
|
$var wire 1 %/ final_acc_upper_all0 $end
|
|
$var wire 16 &/ n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 2048 '/ w_bus [2047:0] $end
|
|
$var wire 2048 (/ x_bus [2047:0] $end
|
|
$var wire 8 )/ y_relu [7:0] $end
|
|
$var wire 8 */ y_none [7:0] $end
|
|
$var wire 256 +/ x_group [255:0] $end
|
|
$var wire 256 ,/ w_group [255:0] $end
|
|
$var wire 16 -/ groups_real [15:0] $end
|
|
$var wire 1 ./ final_acc_upper_all1 $end
|
|
$var wire 1 // final_acc_sign $end
|
|
$var wire 32 0/ final_acc [31:0] $end
|
|
$var wire 32 1/ bias_ext [31:0] $end
|
|
$var wire 32 2/ acc_next [31:0] $end
|
|
$var parameter 32 3/ ACC_WIDTH $end
|
|
$var parameter 2 4/ ACT_NONE $end
|
|
$var parameter 2 5/ ACT_RELU $end
|
|
$var parameter 32 6/ DATA_WIDTH $end
|
|
$var parameter 32 7/ GROUPS $end
|
|
$var parameter 32 8/ GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 9/ N_INPUTS $end
|
|
$var parameter 32 :/ PARALLEL $end
|
|
$var reg 32 ;/ acc [31:0] $end
|
|
$var reg 1 </ busy $end
|
|
$var reg 1 =/ done $end
|
|
$var reg 1 >/ finishing $end
|
|
$var reg 3 ?/ group_index [2:0] $end
|
|
$var reg 8 @/ y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 A/ acc_in [31:0] $end
|
|
$var wire 256 B/ w_bus [255:0] $end
|
|
$var wire 256 C/ x_bus [255:0] $end
|
|
$var wire 32 D/ acc_out [31:0] $end
|
|
$var parameter 32 E/ ACC_WIDTH $end
|
|
$var parameter 32 F/ DATA_WIDTH $end
|
|
$var parameter 32 G/ PARALLEL $end
|
|
$var parameter 32 H/ TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 I/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 J/ acc_in [31:0] $end
|
|
$var wire 8 K/ w [7:0] $end
|
|
$var wire 8 L/ x [7:0] $end
|
|
$var wire 32 M/ product_ext [31:0] $end
|
|
$var wire 16 N/ product [15:0] $end
|
|
$var wire 32 O/ acc_out [31:0] $end
|
|
$var parameter 32 P/ ACC_WIDTH $end
|
|
$var parameter 32 Q/ DATA_WIDTH $end
|
|
$var parameter 64 R/ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 S/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 T/ acc_in [31:0] $end
|
|
$var wire 8 U/ w [7:0] $end
|
|
$var wire 8 V/ x [7:0] $end
|
|
$var wire 32 W/ product_ext [31:0] $end
|
|
$var wire 16 X/ product [15:0] $end
|
|
$var wire 32 Y/ acc_out [31:0] $end
|
|
$var parameter 32 Z/ ACC_WIDTH $end
|
|
$var parameter 32 [/ DATA_WIDTH $end
|
|
$var parameter 64 \/ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 ]/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ^/ acc_in [31:0] $end
|
|
$var wire 8 _/ w [7:0] $end
|
|
$var wire 8 `/ x [7:0] $end
|
|
$var wire 32 a/ product_ext [31:0] $end
|
|
$var wire 16 b/ product [15:0] $end
|
|
$var wire 32 c/ acc_out [31:0] $end
|
|
$var parameter 32 d/ ACC_WIDTH $end
|
|
$var parameter 32 e/ DATA_WIDTH $end
|
|
$var parameter 64 f/ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 g/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 h/ acc_in [31:0] $end
|
|
$var wire 8 i/ w [7:0] $end
|
|
$var wire 8 j/ x [7:0] $end
|
|
$var wire 32 k/ product_ext [31:0] $end
|
|
$var wire 16 l/ product [15:0] $end
|
|
$var wire 32 m/ acc_out [31:0] $end
|
|
$var parameter 32 n/ ACC_WIDTH $end
|
|
$var parameter 32 o/ DATA_WIDTH $end
|
|
$var parameter 64 p/ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 q/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 r/ acc_in [31:0] $end
|
|
$var wire 8 s/ w [7:0] $end
|
|
$var wire 8 t/ x [7:0] $end
|
|
$var wire 32 u/ product_ext [31:0] $end
|
|
$var wire 16 v/ product [15:0] $end
|
|
$var wire 32 w/ acc_out [31:0] $end
|
|
$var parameter 32 x/ ACC_WIDTH $end
|
|
$var parameter 32 y/ DATA_WIDTH $end
|
|
$var parameter 64 z/ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 {/ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 |/ acc_in [31:0] $end
|
|
$var wire 8 }/ w [7:0] $end
|
|
$var wire 8 ~/ x [7:0] $end
|
|
$var wire 32 !0 product_ext [31:0] $end
|
|
$var wire 16 "0 product [15:0] $end
|
|
$var wire 32 #0 acc_out [31:0] $end
|
|
$var parameter 32 $0 ACC_WIDTH $end
|
|
$var parameter 32 %0 DATA_WIDTH $end
|
|
$var parameter 64 &0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 '0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 (0 acc_in [31:0] $end
|
|
$var wire 8 )0 w [7:0] $end
|
|
$var wire 8 *0 x [7:0] $end
|
|
$var wire 32 +0 product_ext [31:0] $end
|
|
$var wire 16 ,0 product [15:0] $end
|
|
$var wire 32 -0 acc_out [31:0] $end
|
|
$var parameter 32 .0 ACC_WIDTH $end
|
|
$var parameter 32 /0 DATA_WIDTH $end
|
|
$var parameter 64 00 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 10 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 20 acc_in [31:0] $end
|
|
$var wire 8 30 w [7:0] $end
|
|
$var wire 8 40 x [7:0] $end
|
|
$var wire 32 50 product_ext [31:0] $end
|
|
$var wire 16 60 product [15:0] $end
|
|
$var wire 32 70 acc_out [31:0] $end
|
|
$var parameter 32 80 ACC_WIDTH $end
|
|
$var parameter 32 90 DATA_WIDTH $end
|
|
$var parameter 64 :0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 ;0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 <0 acc_in [31:0] $end
|
|
$var wire 8 =0 w [7:0] $end
|
|
$var wire 8 >0 x [7:0] $end
|
|
$var wire 32 ?0 product_ext [31:0] $end
|
|
$var wire 16 @0 product [15:0] $end
|
|
$var wire 32 A0 acc_out [31:0] $end
|
|
$var parameter 32 B0 ACC_WIDTH $end
|
|
$var parameter 32 C0 DATA_WIDTH $end
|
|
$var parameter 64 D0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 E0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 F0 acc_in [31:0] $end
|
|
$var wire 8 G0 w [7:0] $end
|
|
$var wire 8 H0 x [7:0] $end
|
|
$var wire 32 I0 product_ext [31:0] $end
|
|
$var wire 16 J0 product [15:0] $end
|
|
$var wire 32 K0 acc_out [31:0] $end
|
|
$var parameter 32 L0 ACC_WIDTH $end
|
|
$var parameter 32 M0 DATA_WIDTH $end
|
|
$var parameter 64 N0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 O0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 P0 acc_in [31:0] $end
|
|
$var wire 8 Q0 w [7:0] $end
|
|
$var wire 8 R0 x [7:0] $end
|
|
$var wire 32 S0 product_ext [31:0] $end
|
|
$var wire 16 T0 product [15:0] $end
|
|
$var wire 32 U0 acc_out [31:0] $end
|
|
$var parameter 32 V0 ACC_WIDTH $end
|
|
$var parameter 32 W0 DATA_WIDTH $end
|
|
$var parameter 64 X0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 Y0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Z0 acc_in [31:0] $end
|
|
$var wire 8 [0 w [7:0] $end
|
|
$var wire 8 \0 x [7:0] $end
|
|
$var wire 32 ]0 product_ext [31:0] $end
|
|
$var wire 16 ^0 product [15:0] $end
|
|
$var wire 32 _0 acc_out [31:0] $end
|
|
$var parameter 32 `0 ACC_WIDTH $end
|
|
$var parameter 32 a0 DATA_WIDTH $end
|
|
$var parameter 64 b0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 c0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 d0 acc_in [31:0] $end
|
|
$var wire 8 e0 w [7:0] $end
|
|
$var wire 8 f0 x [7:0] $end
|
|
$var wire 32 g0 product_ext [31:0] $end
|
|
$var wire 16 h0 product [15:0] $end
|
|
$var wire 32 i0 acc_out [31:0] $end
|
|
$var parameter 32 j0 ACC_WIDTH $end
|
|
$var parameter 32 k0 DATA_WIDTH $end
|
|
$var parameter 64 l0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 m0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 n0 acc_in [31:0] $end
|
|
$var wire 8 o0 w [7:0] $end
|
|
$var wire 8 p0 x [7:0] $end
|
|
$var wire 32 q0 product_ext [31:0] $end
|
|
$var wire 16 r0 product [15:0] $end
|
|
$var wire 32 s0 acc_out [31:0] $end
|
|
$var parameter 32 t0 ACC_WIDTH $end
|
|
$var parameter 32 u0 DATA_WIDTH $end
|
|
$var parameter 64 v0 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 w0 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 x0 acc_in [31:0] $end
|
|
$var wire 8 y0 w [7:0] $end
|
|
$var wire 8 z0 x [7:0] $end
|
|
$var wire 32 {0 product_ext [31:0] $end
|
|
$var wire 16 |0 product [15:0] $end
|
|
$var wire 32 }0 acc_out [31:0] $end
|
|
$var parameter 32 ~0 ACC_WIDTH $end
|
|
$var parameter 32 !1 DATA_WIDTH $end
|
|
$var parameter 64 "1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 #1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 $1 acc_in [31:0] $end
|
|
$var wire 8 %1 w [7:0] $end
|
|
$var wire 8 &1 x [7:0] $end
|
|
$var wire 32 '1 product_ext [31:0] $end
|
|
$var wire 16 (1 product [15:0] $end
|
|
$var wire 32 )1 acc_out [31:0] $end
|
|
$var parameter 32 *1 ACC_WIDTH $end
|
|
$var parameter 32 +1 DATA_WIDTH $end
|
|
$var parameter 64 ,1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[16] $end
|
|
$var parameter 6 -1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 .1 acc_in [31:0] $end
|
|
$var wire 8 /1 w [7:0] $end
|
|
$var wire 8 01 x [7:0] $end
|
|
$var wire 32 11 product_ext [31:0] $end
|
|
$var wire 16 21 product [15:0] $end
|
|
$var wire 32 31 acc_out [31:0] $end
|
|
$var parameter 32 41 ACC_WIDTH $end
|
|
$var parameter 32 51 DATA_WIDTH $end
|
|
$var parameter 64 61 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[17] $end
|
|
$var parameter 6 71 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 81 acc_in [31:0] $end
|
|
$var wire 8 91 w [7:0] $end
|
|
$var wire 8 :1 x [7:0] $end
|
|
$var wire 32 ;1 product_ext [31:0] $end
|
|
$var wire 16 <1 product [15:0] $end
|
|
$var wire 32 =1 acc_out [31:0] $end
|
|
$var parameter 32 >1 ACC_WIDTH $end
|
|
$var parameter 32 ?1 DATA_WIDTH $end
|
|
$var parameter 64 @1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[18] $end
|
|
$var parameter 6 A1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 B1 acc_in [31:0] $end
|
|
$var wire 8 C1 w [7:0] $end
|
|
$var wire 8 D1 x [7:0] $end
|
|
$var wire 32 E1 product_ext [31:0] $end
|
|
$var wire 16 F1 product [15:0] $end
|
|
$var wire 32 G1 acc_out [31:0] $end
|
|
$var parameter 32 H1 ACC_WIDTH $end
|
|
$var parameter 32 I1 DATA_WIDTH $end
|
|
$var parameter 64 J1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[19] $end
|
|
$var parameter 6 K1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 L1 acc_in [31:0] $end
|
|
$var wire 8 M1 w [7:0] $end
|
|
$var wire 8 N1 x [7:0] $end
|
|
$var wire 32 O1 product_ext [31:0] $end
|
|
$var wire 16 P1 product [15:0] $end
|
|
$var wire 32 Q1 acc_out [31:0] $end
|
|
$var parameter 32 R1 ACC_WIDTH $end
|
|
$var parameter 32 S1 DATA_WIDTH $end
|
|
$var parameter 64 T1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[20] $end
|
|
$var parameter 6 U1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 V1 acc_in [31:0] $end
|
|
$var wire 8 W1 w [7:0] $end
|
|
$var wire 8 X1 x [7:0] $end
|
|
$var wire 32 Y1 product_ext [31:0] $end
|
|
$var wire 16 Z1 product [15:0] $end
|
|
$var wire 32 [1 acc_out [31:0] $end
|
|
$var parameter 32 \1 ACC_WIDTH $end
|
|
$var parameter 32 ]1 DATA_WIDTH $end
|
|
$var parameter 64 ^1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[21] $end
|
|
$var parameter 6 _1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 `1 acc_in [31:0] $end
|
|
$var wire 8 a1 w [7:0] $end
|
|
$var wire 8 b1 x [7:0] $end
|
|
$var wire 32 c1 product_ext [31:0] $end
|
|
$var wire 16 d1 product [15:0] $end
|
|
$var wire 32 e1 acc_out [31:0] $end
|
|
$var parameter 32 f1 ACC_WIDTH $end
|
|
$var parameter 32 g1 DATA_WIDTH $end
|
|
$var parameter 64 h1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[22] $end
|
|
$var parameter 6 i1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 j1 acc_in [31:0] $end
|
|
$var wire 8 k1 w [7:0] $end
|
|
$var wire 8 l1 x [7:0] $end
|
|
$var wire 32 m1 product_ext [31:0] $end
|
|
$var wire 16 n1 product [15:0] $end
|
|
$var wire 32 o1 acc_out [31:0] $end
|
|
$var parameter 32 p1 ACC_WIDTH $end
|
|
$var parameter 32 q1 DATA_WIDTH $end
|
|
$var parameter 64 r1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[23] $end
|
|
$var parameter 6 s1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 t1 acc_in [31:0] $end
|
|
$var wire 8 u1 w [7:0] $end
|
|
$var wire 8 v1 x [7:0] $end
|
|
$var wire 32 w1 product_ext [31:0] $end
|
|
$var wire 16 x1 product [15:0] $end
|
|
$var wire 32 y1 acc_out [31:0] $end
|
|
$var parameter 32 z1 ACC_WIDTH $end
|
|
$var parameter 32 {1 DATA_WIDTH $end
|
|
$var parameter 64 |1 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[24] $end
|
|
$var parameter 6 }1 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ~1 acc_in [31:0] $end
|
|
$var wire 8 !2 w [7:0] $end
|
|
$var wire 8 "2 x [7:0] $end
|
|
$var wire 32 #2 product_ext [31:0] $end
|
|
$var wire 16 $2 product [15:0] $end
|
|
$var wire 32 %2 acc_out [31:0] $end
|
|
$var parameter 32 &2 ACC_WIDTH $end
|
|
$var parameter 32 '2 DATA_WIDTH $end
|
|
$var parameter 64 (2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[25] $end
|
|
$var parameter 6 )2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 *2 acc_in [31:0] $end
|
|
$var wire 8 +2 w [7:0] $end
|
|
$var wire 8 ,2 x [7:0] $end
|
|
$var wire 32 -2 product_ext [31:0] $end
|
|
$var wire 16 .2 product [15:0] $end
|
|
$var wire 32 /2 acc_out [31:0] $end
|
|
$var parameter 32 02 ACC_WIDTH $end
|
|
$var parameter 32 12 DATA_WIDTH $end
|
|
$var parameter 64 22 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[26] $end
|
|
$var parameter 6 32 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 42 acc_in [31:0] $end
|
|
$var wire 8 52 w [7:0] $end
|
|
$var wire 8 62 x [7:0] $end
|
|
$var wire 32 72 product_ext [31:0] $end
|
|
$var wire 16 82 product [15:0] $end
|
|
$var wire 32 92 acc_out [31:0] $end
|
|
$var parameter 32 :2 ACC_WIDTH $end
|
|
$var parameter 32 ;2 DATA_WIDTH $end
|
|
$var parameter 64 <2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[27] $end
|
|
$var parameter 6 =2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 >2 acc_in [31:0] $end
|
|
$var wire 8 ?2 w [7:0] $end
|
|
$var wire 8 @2 x [7:0] $end
|
|
$var wire 32 A2 product_ext [31:0] $end
|
|
$var wire 16 B2 product [15:0] $end
|
|
$var wire 32 C2 acc_out [31:0] $end
|
|
$var parameter 32 D2 ACC_WIDTH $end
|
|
$var parameter 32 E2 DATA_WIDTH $end
|
|
$var parameter 64 F2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[28] $end
|
|
$var parameter 6 G2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 H2 acc_in [31:0] $end
|
|
$var wire 8 I2 w [7:0] $end
|
|
$var wire 8 J2 x [7:0] $end
|
|
$var wire 32 K2 product_ext [31:0] $end
|
|
$var wire 16 L2 product [15:0] $end
|
|
$var wire 32 M2 acc_out [31:0] $end
|
|
$var parameter 32 N2 ACC_WIDTH $end
|
|
$var parameter 32 O2 DATA_WIDTH $end
|
|
$var parameter 64 P2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[29] $end
|
|
$var parameter 6 Q2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 R2 acc_in [31:0] $end
|
|
$var wire 8 S2 w [7:0] $end
|
|
$var wire 8 T2 x [7:0] $end
|
|
$var wire 32 U2 product_ext [31:0] $end
|
|
$var wire 16 V2 product [15:0] $end
|
|
$var wire 32 W2 acc_out [31:0] $end
|
|
$var parameter 32 X2 ACC_WIDTH $end
|
|
$var parameter 32 Y2 DATA_WIDTH $end
|
|
$var parameter 64 Z2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[30] $end
|
|
$var parameter 6 [2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 \2 acc_in [31:0] $end
|
|
$var wire 8 ]2 w [7:0] $end
|
|
$var wire 8 ^2 x [7:0] $end
|
|
$var wire 32 _2 product_ext [31:0] $end
|
|
$var wire 16 `2 product [15:0] $end
|
|
$var wire 32 a2 acc_out [31:0] $end
|
|
$var parameter 32 b2 ACC_WIDTH $end
|
|
$var parameter 32 c2 DATA_WIDTH $end
|
|
$var parameter 64 d2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[31] $end
|
|
$var parameter 6 e2 i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 f2 acc_in [31:0] $end
|
|
$var wire 8 g2 w [7:0] $end
|
|
$var wire 8 h2 x [7:0] $end
|
|
$var wire 32 i2 product_ext [31:0] $end
|
|
$var wire 16 j2 product [15:0] $end
|
|
$var wire 32 k2 acc_out [31:0] $end
|
|
$var parameter 32 l2 ACC_WIDTH $end
|
|
$var parameter 32 m2 DATA_WIDTH $end
|
|
$var parameter 64 n2 PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 o2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 p2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 q2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 r2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 s2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 t2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 u2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 v2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 w2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 x2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 y2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 z2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 {2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 |2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 }2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 ~2 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[16] $end
|
|
$var parameter 6 !3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[17] $end
|
|
$var parameter 6 "3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[18] $end
|
|
$var parameter 6 #3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[19] $end
|
|
$var parameter 6 $3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[20] $end
|
|
$var parameter 6 %3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[21] $end
|
|
$var parameter 6 &3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[22] $end
|
|
$var parameter 6 '3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[23] $end
|
|
$var parameter 6 (3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[24] $end
|
|
$var parameter 6 )3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[25] $end
|
|
$var parameter 6 *3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[26] $end
|
|
$var parameter 6 +3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[27] $end
|
|
$var parameter 6 ,3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[28] $end
|
|
$var parameter 6 -3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[29] $end
|
|
$var parameter 6 .3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[30] $end
|
|
$var parameter 6 /3 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[31] $end
|
|
$var parameter 6 03 i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 13 level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 23 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 33 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 43 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 53 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 63 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 73 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 83 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 93 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[8] $end
|
|
$var parameter 5 :3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[9] $end
|
|
$var parameter 5 ;3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[10] $end
|
|
$var parameter 5 <3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[11] $end
|
|
$var parameter 5 =3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[12] $end
|
|
$var parameter 5 >3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[13] $end
|
|
$var parameter 5 ?3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[14] $end
|
|
$var parameter 5 @3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[15] $end
|
|
$var parameter 5 A3 node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 B3 level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 C3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 D3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 E3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 F3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 G3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 H3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 I3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 J3 node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 K3 level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 L3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 M3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 N3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 O3 node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 P3 level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 Q3 node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 R3 node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[4] $end
|
|
$var parameter 4 S3 level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 T3 node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope task run_layer $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$comment Show the parameter values. $end
|
|
$dumpall
|
|
b0 T3
|
|
b100 S3
|
|
b1 R3
|
|
b0 Q3
|
|
b11 P3
|
|
b11 O3
|
|
b10 N3
|
|
b1 M3
|
|
b0 L3
|
|
b10 K3
|
|
b111 J3
|
|
b110 I3
|
|
b101 H3
|
|
b100 G3
|
|
b11 F3
|
|
b10 E3
|
|
b1 D3
|
|
b0 C3
|
|
b1 B3
|
|
b1111 A3
|
|
b1110 @3
|
|
b1101 ?3
|
|
b1100 >3
|
|
b1011 =3
|
|
b1010 <3
|
|
b1001 ;3
|
|
b1000 :3
|
|
b111 93
|
|
b110 83
|
|
b101 73
|
|
b100 63
|
|
b11 53
|
|
b10 43
|
|
b1 33
|
|
b0 23
|
|
b0 13
|
|
b11111 03
|
|
b11110 /3
|
|
b11101 .3
|
|
b11100 -3
|
|
b11011 ,3
|
|
b11010 +3
|
|
b11001 *3
|
|
b11000 )3
|
|
b10111 (3
|
|
b10110 '3
|
|
b10101 &3
|
|
b10100 %3
|
|
b10011 $3
|
|
b10010 #3
|
|
b10001 "3
|
|
b10000 !3
|
|
b1111 ~2
|
|
b1110 }2
|
|
b1101 |2
|
|
b1100 {2
|
|
b1011 z2
|
|
b1010 y2
|
|
b1001 x2
|
|
b1000 w2
|
|
b111 v2
|
|
b110 u2
|
|
b101 t2
|
|
b100 s2
|
|
b11 r2
|
|
b10 q2
|
|
b1 p2
|
|
b0 o2
|
|
b10000 n2
|
|
b1000 m2
|
|
b100000 l2
|
|
b11111 e2
|
|
b10000 d2
|
|
b1000 c2
|
|
b100000 b2
|
|
b11110 [2
|
|
b10000 Z2
|
|
b1000 Y2
|
|
b100000 X2
|
|
b11101 Q2
|
|
b10000 P2
|
|
b1000 O2
|
|
b100000 N2
|
|
b11100 G2
|
|
b10000 F2
|
|
b1000 E2
|
|
b100000 D2
|
|
b11011 =2
|
|
b10000 <2
|
|
b1000 ;2
|
|
b100000 :2
|
|
b11010 32
|
|
b10000 22
|
|
b1000 12
|
|
b100000 02
|
|
b11001 )2
|
|
b10000 (2
|
|
b1000 '2
|
|
b100000 &2
|
|
b11000 }1
|
|
b10000 |1
|
|
b1000 {1
|
|
b100000 z1
|
|
b10111 s1
|
|
b10000 r1
|
|
b1000 q1
|
|
b100000 p1
|
|
b10110 i1
|
|
b10000 h1
|
|
b1000 g1
|
|
b100000 f1
|
|
b10101 _1
|
|
b10000 ^1
|
|
b1000 ]1
|
|
b100000 \1
|
|
b10100 U1
|
|
b10000 T1
|
|
b1000 S1
|
|
b100000 R1
|
|
b10011 K1
|
|
b10000 J1
|
|
b1000 I1
|
|
b100000 H1
|
|
b10010 A1
|
|
b10000 @1
|
|
b1000 ?1
|
|
b100000 >1
|
|
b10001 71
|
|
b10000 61
|
|
b1000 51
|
|
b100000 41
|
|
b10000 -1
|
|
b10000 ,1
|
|
b1000 +1
|
|
b100000 *1
|
|
b1111 #1
|
|
b10000 "1
|
|
b1000 !1
|
|
b100000 ~0
|
|
b1110 w0
|
|
b10000 v0
|
|
b1000 u0
|
|
b100000 t0
|
|
b1101 m0
|
|
b10000 l0
|
|
b1000 k0
|
|
b100000 j0
|
|
b1100 c0
|
|
b10000 b0
|
|
b1000 a0
|
|
b100000 `0
|
|
b1011 Y0
|
|
b10000 X0
|
|
b1000 W0
|
|
b100000 V0
|
|
b1010 O0
|
|
b10000 N0
|
|
b1000 M0
|
|
b100000 L0
|
|
b1001 E0
|
|
b10000 D0
|
|
b1000 C0
|
|
b100000 B0
|
|
b1000 ;0
|
|
b10000 :0
|
|
b1000 90
|
|
b100000 80
|
|
b111 10
|
|
b10000 00
|
|
b1000 /0
|
|
b100000 .0
|
|
b110 '0
|
|
b10000 &0
|
|
b1000 %0
|
|
b100000 $0
|
|
b101 {/
|
|
b10000 z/
|
|
b1000 y/
|
|
b100000 x/
|
|
b100 q/
|
|
b10000 p/
|
|
b1000 o/
|
|
b100000 n/
|
|
b11 g/
|
|
b10000 f/
|
|
b1000 e/
|
|
b100000 d/
|
|
b10 ]/
|
|
b10000 \/
|
|
b1000 [/
|
|
b100000 Z/
|
|
b1 S/
|
|
b10000 R/
|
|
b1000 Q/
|
|
b100000 P/
|
|
b0 I/
|
|
b101 H/
|
|
b100000 G/
|
|
b1000 F/
|
|
b100000 E/
|
|
b100000 :/
|
|
b100000000 9/
|
|
b11 8/
|
|
b1000 7/
|
|
b1000 6/
|
|
b1 5/
|
|
b0 4/
|
|
b100000 3/
|
|
b11 ~.
|
|
b0 }.
|
|
b100 |.
|
|
b1 {.
|
|
b0 z.
|
|
b11 y.
|
|
b11 x.
|
|
b10 w.
|
|
b1 v.
|
|
b0 u.
|
|
b10 t.
|
|
b111 s.
|
|
b110 r.
|
|
b101 q.
|
|
b100 p.
|
|
b11 o.
|
|
b10 n.
|
|
b1 m.
|
|
b0 l.
|
|
b1 k.
|
|
b1111 j.
|
|
b1110 i.
|
|
b1101 h.
|
|
b1100 g.
|
|
b1011 f.
|
|
b1010 e.
|
|
b1001 d.
|
|
b1000 c.
|
|
b111 b.
|
|
b110 a.
|
|
b101 `.
|
|
b100 _.
|
|
b11 ^.
|
|
b10 ].
|
|
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