FPGA-Neural

T

micheleandClaude Sonnet 5 3dd75e9e0d test: certify memory subsystem addressing (C.3)

int8_memory_access.v byte<->word conversion and byte-lane selection:
exhaustive 2048-address test + 6 real read/write round-trips through
the FSM handshake. 2054/2054 checks, 0 mismatches, after fixing two
bugs in the test harness itself (a same-timestep race reading a
non-blocking update one iteration late, and a behavioral memory stub
that ignored byte-lane enables on write) -- both documented as
test-side, not RTL, issues.

memory_interface.v and psram_controller.v not re-verified from
scratch: cited against coverage already established/re-confirmed
earlier in this same session (page-mode/tCEM against the ISSI
datasheet, a real pre-existing power-up request-loss bug found and
fixed), re-run clean via the Phase 0 regression harness rather than
trusted from WORKLOG text alone.

Full regression: 39/39 real tests pass.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-04 14:33:05 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

test: certify memory subsystem addressing (C.3)

2026-09-04 14:33:05 +02:00

rtl

fix: make flash SPI bus electrically independent, drop USRMCLK/CCLK reuse (Phase F7)

2026-09-04 10:16:31 +02:00

sim

test: certify memory subsystem addressing (C.3)