micheleandClaude Sonnet 5
3dd75e9e0d
int8_memory_access.v byte<->word conversion and byte-lane selection: exhaustive 2048-address test + 6 real read/write round-trips through the FSM handshake. 2054/2054 checks, 0 mismatches, after fixing two bugs in the test harness itself (a same-timestep race reading a non-blocking update one iteration late, and a behavioral memory stub that ignored byte-lane enables on write) -- both documented as test-side, not RTL, issues. memory_interface.v and psram_controller.v not re-verified from scratch: cited against coverage already established/re-confirmed earlier in this same session (page-mode/tCEM against the ISSI datasheet, a real pre-existing power-up request-loss bug found and fixed), re-run clean via the Phase 0 regression harness rather than trusted from WORKLOG text alone. Full regression: 39/39 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1585 lines
28 KiB
Plaintext
1585 lines
28 KiB
Plaintext
$date
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Fri Sep 4 14:31:28 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 8 ! y [7:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 2 % ACT_NONE $end
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$var parameter 2 & ACT_RELU $end
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$var parameter 32 ' DATA_WIDTH $end
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$var parameter 32 ( N_INPUTS $end
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$var parameter 32 ) PARALLEL $end
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$var reg 2 * activation [1:0] $end
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$var reg 8 + bias [7:0] $end
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$var reg 1 , clk $end
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$var reg 16 - n_inputs_real [15:0] $end
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$var reg 1 . rst $end
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$var reg 1 / start $end
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$var reg 256 0 w_bus [255:0] $end
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$var reg 256 1 x_bus [255:0] $end
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$var integer 32 2 cycles_full [31:0] $end
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$var integer 32 3 cycles_reduced [31:0] $end
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$var integer 32 4 errors [31:0] $end
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$var integer 32 5 i [31:0] $end
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$var integer 32 6 t_done [31:0] $end
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$var integer 32 7 t_start [31:0] $end
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$scope module dut $end
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$var wire 2 8 activation [1:0] $end
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$var wire 8 9 bias [7:0] $end
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$var wire 1 , clk $end
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$var wire 1 : final_acc_in_range $end
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$var wire 1 ; final_acc_le_zero $end
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$var wire 1 < final_acc_upper_all0 $end
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$var wire 16 = n_inputs_real [15:0] $end
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$var wire 1 . rst $end
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$var wire 1 / start $end
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$var wire 256 > w_bus [255:0] $end
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$var wire 256 ? x_bus [255:0] $end
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$var wire 8 @ y_relu [7:0] $end
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$var wire 8 A y_none [7:0] $end
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$var wire 64 B x_group [63:0] $end
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$var wire 64 C w_group [63:0] $end
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$var wire 16 D groups_real [15:0] $end
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$var wire 1 E final_acc_upper_all1 $end
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$var wire 1 F final_acc_sign $end
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$var wire 32 G final_acc [31:0] $end
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$var wire 32 H bias_ext [31:0] $end
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$var wire 32 I acc_next [31:0] $end
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$var parameter 32 J ACC_WIDTH $end
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$var parameter 2 K ACT_NONE $end
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$var parameter 2 L ACT_RELU $end
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$var parameter 32 M DATA_WIDTH $end
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$var parameter 32 N GROUPS $end
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$var parameter 32 O GROUP_INDEX_WIDTH $end
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$var parameter 32 P N_INPUTS $end
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$var parameter 32 Q PARALLEL $end
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$var reg 32 R acc [31:0] $end
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$var reg 1 # busy $end
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$var reg 1 " done $end
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$var reg 1 S finishing $end
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$var reg 2 T group_index [1:0] $end
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$var reg 8 U y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 V acc_in [31:0] $end
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$var wire 64 W w_bus [63:0] $end
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$var wire 64 X x_bus [63:0] $end
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$var wire 32 Y acc_out [31:0] $end
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$var parameter 32 Z ACC_WIDTH $end
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$var parameter 32 [ DATA_WIDTH $end
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$var parameter 32 \ PARALLEL $end
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$var parameter 32 ] TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 ^ i $end
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$scope module u_mac $end
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$var wire 32 _ acc_in [31:0] $end
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$var wire 8 ` w [7:0] $end
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$var wire 8 a x [7:0] $end
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$var wire 32 b product_ext [31:0] $end
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$var wire 16 c product [15:0] $end
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$var wire 32 d acc_out [31:0] $end
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$var parameter 32 e ACC_WIDTH $end
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$var parameter 32 f DATA_WIDTH $end
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$var parameter 64 g PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 h i $end
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$scope module u_mac $end
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$var wire 32 i acc_in [31:0] $end
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$var wire 8 j w [7:0] $end
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$var wire 8 k x [7:0] $end
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$var wire 32 l product_ext [31:0] $end
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$var wire 16 m product [15:0] $end
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$var wire 32 n acc_out [31:0] $end
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$var parameter 32 o ACC_WIDTH $end
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$var parameter 32 p DATA_WIDTH $end
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$var parameter 64 q PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 r i $end
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$scope module u_mac $end
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$var wire 32 s acc_in [31:0] $end
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$var wire 8 t w [7:0] $end
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$var wire 8 u x [7:0] $end
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$var wire 32 v product_ext [31:0] $end
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$var wire 16 w product [15:0] $end
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$var wire 32 x acc_out [31:0] $end
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$var parameter 32 y ACC_WIDTH $end
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$var parameter 32 z DATA_WIDTH $end
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$var parameter 64 { PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 | i $end
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$scope module u_mac $end
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$var wire 32 } acc_in [31:0] $end
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$var wire 8 ~ w [7:0] $end
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$var wire 8 !" x [7:0] $end
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$var wire 32 "" product_ext [31:0] $end
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$var wire 16 #" product [15:0] $end
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$var wire 32 $" acc_out [31:0] $end
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$var parameter 32 %" ACC_WIDTH $end
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$var parameter 32 &" DATA_WIDTH $end
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$var parameter 64 '" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 (" i $end
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$scope module u_mac $end
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$var wire 32 )" acc_in [31:0] $end
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$var wire 8 *" w [7:0] $end
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$var wire 8 +" x [7:0] $end
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$var wire 32 ," product_ext [31:0] $end
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$var wire 16 -" product [15:0] $end
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$var wire 32 ." acc_out [31:0] $end
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$var parameter 32 /" ACC_WIDTH $end
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$var parameter 32 0" DATA_WIDTH $end
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$var parameter 64 1" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 2" i $end
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$scope module u_mac $end
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$var wire 32 3" acc_in [31:0] $end
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$var wire 8 4" w [7:0] $end
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$var wire 8 5" x [7:0] $end
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$var wire 32 6" product_ext [31:0] $end
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$var wire 16 7" product [15:0] $end
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$var wire 32 8" acc_out [31:0] $end
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$var parameter 32 9" ACC_WIDTH $end
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$var parameter 32 :" DATA_WIDTH $end
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$var parameter 64 ;" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 <" i $end
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$scope module u_mac $end
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$var wire 32 =" acc_in [31:0] $end
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$var wire 8 >" w [7:0] $end
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$var wire 8 ?" x [7:0] $end
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$var wire 32 @" product_ext [31:0] $end
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$var wire 16 A" product [15:0] $end
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$var wire 32 B" acc_out [31:0] $end
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$var parameter 32 C" ACC_WIDTH $end
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$var parameter 32 D" DATA_WIDTH $end
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$var parameter 64 E" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 F" i $end
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$scope module u_mac $end
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$var wire 32 G" acc_in [31:0] $end
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$var wire 8 H" w [7:0] $end
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$var wire 8 I" x [7:0] $end
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$var wire 32 J" product_ext [31:0] $end
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$var wire 16 K" product [15:0] $end
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$var wire 32 L" acc_out [31:0] $end
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$var parameter 32 M" ACC_WIDTH $end
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$var parameter 32 N" DATA_WIDTH $end
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$var parameter 64 O" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 P" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 Q" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 R" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 S" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 T" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[5] $end
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$var parameter 4 U" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[6] $end
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$var parameter 4 V" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[7] $end
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$var parameter 4 W" i $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[0] $end
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$var parameter 2 X" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 Y" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 Z" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 [" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 \" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[1] $end
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$var parameter 2 ]" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 ^" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 _" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[2] $end
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$var parameter 3 `" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 a" node $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope task run_neuron $end
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$upscope $end
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$scope task test_1 $end
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$upscope $end
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$scope task test_2 $end
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$upscope $end
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$scope task test_3 $end
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$upscope $end
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$scope task test_4 $end
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$upscope $end
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$scope task test_5 $end
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$upscope $end
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$scope task test_6 $end
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$upscope $end
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$scope task test_7 $end
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$var reg 1 b" pass_7 $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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b0 a"
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b10 `"
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b1 _"
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b0 ^"
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b1 ]"
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|
b11 \"
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|
b10 ["
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|
b1 Z"
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|
b0 Y"
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|
b0 X"
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|
b111 W"
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|
b110 V"
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b101 U"
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|
b100 T"
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|
b11 S"
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|
b10 R"
|
|
b1 Q"
|
|
b0 P"
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|
b10000 O"
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|
b1000 N"
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|
b100000 M"
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|
b111 F"
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b10000 E"
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b1000 D"
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b100000 C"
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b110 <"
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|
b10000 ;"
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|
b1000 :"
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b100000 9"
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|
b101 2"
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b10000 1"
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b1000 0"
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b100000 /"
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b100 ("
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|
b10000 '"
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b1000 &"
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b100000 %"
|
|
b11 |
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b10000 {
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b1000 z
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b100000 y
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|
b10 r
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b10000 q
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b1000 p
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|
b100000 o
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|
b1 h
|
|
b10000 g
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|
b1000 f
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|
b100000 e
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|
b0 ^
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|
b11 ]
|
|
b1000 \
|
|
b1000 [
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b100000 Z
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b1000 Q
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b100000 P
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b10 O
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|
b100 N
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b1000 M
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|
b1 L
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|
b0 K
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b100000 J
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b1000 )
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b100000 (
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b1000 '
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b1 &
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b0 %
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b100000 $
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$end
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#0
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$dumpvars
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xb"
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bx L"
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bx K"
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bx J"
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bx I"
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bx H"
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b0 G"
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bx B"
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bx A"
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bx @"
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bx ?"
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bx >"
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b0 ="
|
|
bx 8"
|
|
bx 7"
|
|
bx 6"
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bx 5"
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bx 4"
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b0 3"
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|
bx ."
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bx -"
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|
bx ,"
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bx +"
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bx *"
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|
b0 )"
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|
bx $"
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|
bx #"
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bx ""
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bx !"
|
|
bx ~
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|
b0 }
|
|
bx x
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bx w
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|
bx v
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|
bx u
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|
bx t
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|
b0 s
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bx n
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|
bx m
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bx l
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bx k
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|
bx j
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|
b0 i
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|
bx d
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bx c
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|
bx b
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|
bx a
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|
bx `
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|
b0 _
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|
bx Y
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|
bx X
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|
bx W
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|
bx V
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|
bx U
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|
bx T
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|
xS
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|
bx R
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bx I
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|
b0 H
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|
bx G
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|
xF
|
|
xE
|
|
b100 D
|
|
bx C
|
|
bx B
|
|
bx A
|
|
bx @
|
|
b0 ?
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|
b0 >
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|
b100000 =
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x<
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|
x;
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|
x:
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b0 9
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|
b1 8
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|
bx 7
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|
bx 6
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|
bx 5
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|
b0 4
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|
bx 3
|
|
bx 2
|
|
b0 1
|
|
b0 0
|
|
0/
|
|
1.
|
|
b100000 -
|
|
0,
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|
b0 +
|
|
b1 *
|
|
x#
|
|
x"
|
|
bx !
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|
$end
|
|
#5000
|
|
b0 I
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|
b0 Y
|
|
b0 d
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|
b0 n
|
|
b0 x
|
|
b0 $"
|
|
b0 ."
|
|
b0 8"
|
|
b0 B"
|
|
b0 L"
|
|
b0 A
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|
1:
|
|
b0 @
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|
b0 b
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|
b0 l
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|
b0 v
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|
b0 ""
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|
b0 ,"
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b0 6"
|
|
b0 @"
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b0 J"
|
|
1<
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|
1;
|
|
b0 c
|
|
b0 a
|
|
b0 m
|
|
b0 k
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|
b0 w
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|
b0 u
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|
b0 #"
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b0 !"
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b0 -"
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|
b0 +"
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|
b0 7"
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|
b0 5"
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|
b0 A"
|
|
b0 ?"
|
|
b0 K"
|
|
b0 I"
|
|
b0 `
|
|
b0 j
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|
b0 t
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|
b0 ~
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|
b0 *"
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b0 4"
|
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b0 >"
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b0 H"
|
|
0F
|
|
0E
|
|
b0 B
|
|
b0 X
|
|
b0 C
|
|
b0 W
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|
0S
|
|
0"
|
|
0#
|
|
b0 !
|
|
b0 U
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|
b0 G
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|
b0 R
|
|
b0 V
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b0 T
|
|
1,
|
|
#10000
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|
0,
|
|
#15000
|
|
b1 @
|
|
0;
|
|
b1 A
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|
b10 x
|
|
b10 v
|
|
b11111111111111111111111111111100 n
|
|
b11111111111111111111111111111100 l
|
|
b100 I
|
|
b100 Y
|
|
b110 d
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|
b110 b
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|
b10 w
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|
b1 t
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|
b10 u
|
|
b1111111111111100 m
|
|
b11111111 j
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|
b100 k
|
|
b110 c
|
|
b10 `
|
|
b11 a
|
|
b1 G
|
|
b1 H
|
|
b11111111100000010 C
|
|
b11111111100000010 W
|
|
b11111111100000010 0
|
|
b11111111100000010 >
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|
b100000010000000011 B
|
|
b100000010000000011 X
|
|
b100000010000000011 1
|
|
b100000010000000011 ?
|
|
b1 +
|
|
b1 9
|
|
0.
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|
1,
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|
#20000
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|
0,
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|
#25000
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|
1#
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|
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