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FPGA-Neural/sim/int8_memory_access.vcd
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micheleandClaude Sonnet 5 3dd75e9e0d test: certify memory subsystem addressing (C.3) 
int8_memory_access.v byte<->word conversion and byte-lane selection:
exhaustive 2048-address test + 6 real read/write round-trips through
the FSM handshake. 2054/2054 checks, 0 mismatches, after fixing two
bugs in the test harness itself (a same-timestep race reading a
non-blocking update one iteration late, and a behavioral memory stub
that ignored byte-lane enables on write) -- both documented as
test-side, not RTL, issues.

memory_interface.v and psram_controller.v not re-verified from
scratch: cited against coverage already established/re-confirmed
earlier in this same session (page-mode/tCEM against the ISSI
datasheet, a real pre-existing power-up request-loss bug found and
fixed), re-run clean via the Phase 0 regression harness rather than
trusted from WORKLOG text alone.

Full regression: 39/39 real tests pass.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-04 14:33:05 +02:00

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$date
Fri Sep 4 14:31:15 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 16 ! mem_rdata [15:0] $end
$var wire 1 " mem_ready $end
$var wire 1 # ready $end
$var wire 8 $ rdata [7:0] $end
$var wire 1 % mem_wr $end
$var wire 16 & mem_wdata [15:0] $end
$var wire 1 ' mem_ub_n $end
$var wire 1 ( mem_req $end
$var wire 1 ) mem_lb_n $end
$var wire 23 * mem_addr [22:0] $end
$var parameter 32 + ADDR_WIDTH $end
$var real 1 , CLK_PERIOD $end
$var reg 23 - addr [22:0] $end
$var reg 1 . clk $end
$var reg 16 / model_rdata [15:0] $end
$var reg 1 0 model_ready $end
$var reg 1 1 req $end
$var reg 1 2 rst $end
$var reg 8 3 wdata [7:0] $end
$var reg 1 4 wr $end
$var integer 32 5 i [31:0] $end
$scope module dut $end
$var wire 23 6 addr [22:0] $end
$var wire 1 . clk $end
$var wire 16 7 mem_rdata [15:0] $end
$var wire 1 " mem_ready $end
$var wire 1 1 req $end
$var wire 1 2 rst $end
$var wire 8 8 wdata [7:0] $end
$var wire 1 4 wr $end
$var parameter 32 9 ADDR_WIDTH $end
$var parameter 2 : STATE_IDLE $end
$var parameter 2 ; STATE_WAIT $end
$var reg 23 < addr_reg [22:0] $end
$var reg 23 = mem_addr [22:0] $end
$var reg 1 ) mem_lb_n $end
$var reg 1 ( mem_req $end
$var reg 1 ' mem_ub_n $end
$var reg 16 > mem_wdata [15:0] $end
$var reg 1 % mem_wr $end
$var reg 8 ? rdata [7:0] $end
$var reg 1 # ready $end
$var reg 2 @ state [1:0] $end
$upscope $end
$scope task read_byte $end
$var reg 23 A byte_addr [22:0] $end
$var reg 8 B expected [7:0] $end
$upscope $end
$scope task write_byte $end
$var reg 23 C byte_addr [22:0] $end
$var reg 8 D data [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1 ;
b0 :
b10111 9
r12.5 ,
b10111 +
$end
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