micheleandClaude Sonnet 5
3cdaeaee35
Post-M10, user-requested final benchmark campaign: 6 realistic workloads (16-256 independent neurons in a shared-input dense-layer shape, a random-seeded 2-layer network with real cross-node PSRAM forwarding, and a 6-node 2-hop dependency diamond) x 4 concurrency levels (N_SLOTS=1/2/4/8) through the real, full neural_multiprocessor system (real V1 PSRAM chain, real slot_mem_arbiter). 24/24 runs PASS bit-exact against a software golden model (11,520 individual neuron/ node checks, zero mismatches). Three real bugs found and fixed during the campaign itself (ERR-0009): 1. neural_director.v (M5) had a real RTL bug at N_SLOTS=1 ($clog2(1)=0 makes a replication expression illegal) - never caught because M5-M10 only ever tested N_SLOTS=2/4/8. Fixed with a width-agnostic '0 literal; M5's own testbench re-verified unaffected. 2/3. Two testbench sizing bugs in tb_benchmark_suite.v itself (psram_model DEPTH too small for the Large workload's address range; N_NODES too small for the Stress workload's node-id range, causing a real deadlock via node-id wraparound colliding with an already-DISPATCHED node - a real, honest consequence of DEC-0008's own "no node-slot reclamation" design choice). Headline finding: real parallel scaling is essentially flat beyond N_SLOTS=2 - the single shared PSRAM port saturates at ~91% utilization regardless of slot count, so memory-bound workloads gain only 1.05-1.06x real speedup from N=1 to N=8. Once real POST-P&R Fmax degradation is also factored in, N_SLOTS=4 is measurably 21% SLOWER in real wall-clock time than N_SLOTS=1 for the largest workload tested. N_SLOTS=2 is recommended as the default (DEC-0014, superseding DEC-0012's resource-only "N_SLOTS=8 ceiling" framing for general use). Full 21-section report (every number classified THEORETICAL/ SIMULATED/POST-P&R MEASURED/DERIVED, per the user's own methodology requirements): hardware/v2/docs/benchmarks/ final-benchmark.md Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0014)/ experiments (EXP-0014)/errors (ERR-0009)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
100 lines
5.5 KiB
Plaintext
100 lines
5.5 KiB
Plaintext
# V2 synthesis log -- solo append, mai troncato/sovrascritto (vedi README.md)
|
|
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
|
|
|
|
[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
|
|
LUT: 55 FF: 533 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 96
|
|
CHECK: 0 problems. 36 warnings, all "multiple conflicting drivers for
|
|
neural_processor.\gi" -- benign Yosys quirk for an `integer` used as
|
|
a synthesizable for-loop index in stage 0's unrolled always block,
|
|
not a real multi-driver conflict (cross-verified functionally
|
|
correct on 2 independent simulators). Log: hardware/v2/synthesis/
|
|
neural_processor_p8/yosys.log
|
|
|
|
[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
|
|
LUT: 49 FF: 509 DSP(MULT18X18D): 8 BRAM: 0 CCU2C: 88
|
|
CHECK: 0 problems, same 36 benign warnings as EXP-0001.
|
|
Log: hardware/v2/synthesis/neural_processor_p8_acc24/yosys.log
|
|
|
|
[2026-09-05] EXP-0003 -- neural_processor_array via
|
|
harness_neural_processor_array.v (synthesis-only wrapper, see
|
|
errors.log ERR-0005), N_PROCESSORS in {1,2,4,8}, P_IN=8
|
|
N=1: LUT=59 FF=409 MULT18X18D=8 CCU2C=96
|
|
N=2: LUT=106 FF=786 MULT18X18D=16 CCU2C=192
|
|
N=4: LUT=207 FF=1540 MULT18X18D=32 CCU2C=384
|
|
N=8: LUT=374 FF=3048 MULT18X18D=64 CCU2C=768
|
|
CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
|
|
N confirms no unintended cross-processor resource sharing (a first,
|
|
flawed harness attempt fed identical data to every processor/lane
|
|
and Yosys silently deduplicated down to 1x regardless of N -- caught
|
|
by checking for exactly this linearity before trusting the numbers).
|
|
|
|
[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
|
|
2 depths each
|
|
activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
|
|
weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
|
|
result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
|
|
CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
|
|
fallback). weight_buffer's DP16KD count does NOT drop with depth
|
|
(width-bound, not depth-bound -- see decisions.log / benchmark.log).
|
|
|
|
[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone)
|
|
LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no
|
|
multiplication in this module). CHECK: 0 problems.
|
|
|
|
[2026-09-05] EXP-0006 -- neural_director (N_SLOTS=4, standalone)
|
|
LUT4=382 TRELLIS_FF=366 CCU2C=4 DSP=0. CHECK: 0 problems.
|
|
|
|
[2026-09-05] EXP-0007 -- dependency_manager (N_NODES=16, MAX_DEPS=4)
|
|
LUT4=763 TRELLIS_FF=474 CCU2C=0 DSP=0. CHECK: 0 problems.
|
|
|
|
[2026-09-05] EXP-0008 -- dataflow_core (M7 full integration, via
|
|
harness_dataflow_core.v -- see errors.log ERR-0005 for why a harness
|
|
is needed: bare per-slot Memory Backend Interface ports alone total
|
|
280 bits at N_SLOTS=4, exceeding the LFE5U-45F-8BG381's ~245 TRELLIS_IO
|
|
budget)
|
|
N_SLOTS=2: LUT4=2127 CCU2C=248 TRELLIS_FF=2505 MULT18X18D=16 DP16KD=0
|
|
N_SLOTS=4: LUT4=3953 CCU2C=500 TRELLIS_FF=4688 MULT18X18D=32 DP16KD=0
|
|
CHECK: 0 problems on both configs (same 32 benign "multiple conflicting
|
|
drivers for ...neural_processor.\gi" warnings per neural_processor
|
|
instance already documented in EXP-0001 -- an `integer` for-loop
|
|
index shared across two of neural_processor's own always blocks, not
|
|
a real multi-driver conflict). DP16KD=0 on both is expected: M3's
|
|
BRAM-backed buffers (activation/weight/result_buffer) are
|
|
deliberately NOT instantiated inside dataflow_core yet (decisions.log
|
|
DEC-0009). DSP scales exactly 8/slot (matches P_IN=8, consistent with
|
|
every prior per-processor DSP measurement since M1/M2).
|
|
|
|
[2026-09-05] EXP-0009 -- neural_multiprocessor (M8, N_SLOTS=2, real
|
|
standalone top-level synthesis -- no timing harness needed: real PSRAM
|
|
pins replace dataflow_core's wide per-slot arrays, total 157 port bits,
|
|
well under the LFE5U-45F-8BG381's ~245 TRELLIS_IO budget)
|
|
LUT4=3145 CCU2C=388 TRELLIS_FF=3659 MULT18X18D=16 DP16KD=0
|
|
TRELLIS_DPR16X4=45 (small LUT-based distributed RAM, inferred from
|
|
neural_director's shallow QUEUE_DEPTH-entry job queue -- not BRAM,
|
|
same primitive class already seen in M7's own harness stat)
|
|
$_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
|
|
from V1's own unmodified psram_controller.v)
|
|
CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
|
|
...neural_processor.\gi" warnings documented since EXP-0001).
|
|
|
|
[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (M10, "numero
|
|
processor" axis, via harness_dataflow_core.v, extending M7's own
|
|
N_SLOTS=2/4 sweep to the real DSP ceiling predicted by DEC-0005)
|
|
LUT4=6439 CCU2C=996 TRELLIS_FF=9053 MULT18X18D=64 (64/72=88.9% of
|
|
the LFE5U-45F's total DSP budget -- matches DEC-0005's M2-era
|
|
prediction almost exactly, since dataflow_core's per-slot DSP cost
|
|
is just neural_processor's own P_IN=8 DSP cost x N_SLOTS)
|
|
DP16KD=0 (expected, DEC-0009). CHECK: 0 problems (same benign
|
|
"multiple conflicting drivers" warnings as every other neural_processor
|
|
instantiation since EXP-0001).
|
|
|
|
[2026-09-05] EXP-0014 -- neural_multiprocessor N_SLOTS=1 and N_SLOTS=4
|
|
(final benchmark campaign, real standalone top-level synthesis, no
|
|
harness needed -- same 157-pin real-PSRAM-pin methodology as N_SLOTS=2,
|
|
EXP-0009)
|
|
N_SLOTS=1: LUT4=2642 CCU2C=200 TRELLIS_FF=2240 MULT18X18D=8 DP16KD=0
|
|
N_SLOTS=4: LUT4=7552 CCU2C=768 TRELLIS_FF=6495 MULT18X18D=32 DP16KD=0
|
|
(N_SLOTS=2 reference, EXP-0009: LUT4=4191 CCU2C=388 FF=3659 DSP=16 DP16KD=0)
|
|
CHECK: 0 problems on both, same benign warnings as every other
|
|
neural_processor instantiation since EXP-0001.
|