FPGA-Neural

T

micheleandClaude Sonnet 5 376ccb6ee2 docs: capture two more exploratory scaling directions (BRAM cache, ESP32-side scheduling)

S5.6.1: opportunistic BRAM cache for activation tiles - exploits real,
currently 0%-utilized Block RAM to catch whatever locality the workload
happens to have, without committing to a specific reuse pattern the way
the systolic direction does. No cache-invalidation problem given the
current write-once-before-job protocol.

S5.6.2: host-side (ESP32) job-queue reordering - a software-only
"DDRManager" upstream of ddr_prefetch_mgr.v, grouping jobs with nearby
DDR3 addresses before submission to reduce row-switch cost with zero
RTL and zero timing-margin risk. Both marked exploratory, not decided,
not built - same as S5.6's systolic direction.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 13:22:17 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: capture two more exploratory scaling directions (BRAM cache, ESP32-side scheduling)

2026-09-20 13:22:17 +02:00

hardware

feat: DDRManager phase 1 - single-slot look-ahead activation prefetch (EXP-0083)

2026-09-20 10:59:45 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze