micheleandClaude Sonnet 5
344e798ad5
Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the now-closed 32-bit DDR3 channel (EXP-0086), per this project's own standing plan. Real result: the 2.86% benefit measured at the old 16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT: 100656.6835ns -- a 0.0064% regression, statistically a wash). The wider channel's lower per-tile latency already absorbs the gap the look-ahead prefetch used to hide. Kept wired in for correctness/ timing-neutrality (real P&R already signs off with it included), but it's no longer a real performance win. Updated docs/ARCHITECTURE_ ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly. Found and fixed 3 real testbench/simulation-setup bugs along the way: - tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the current real, closed 3225ps (EXP-0086). - tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast syntax, invalid for xvlog's default plain-Verilog mode -- fixed via an intermediate 8-bit reg. - Building a fresh sim_1 fileset needs the real MIG simulation dependency set added explicitly (mig_7series_0_mig.v is marked USED_IN_SIMULATION=0 in the project since testbenches bypass the public wrapper); verilog_define is a fileset-level property, not per-file, in this Vivado version. New measurement-only fork (not part of the real synthesis target, per fork-before-promote discipline): packed_slot_noprefetch.v + tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct per-tile activation-fetch sequencing for a fair A/B baseline. Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3 x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3- WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator flagged as needing a custom-programmed order, no off-the-shelf SKU at the required 310.077MHz) and a consolidated, board-layout-ready pinout extract of PHYSICAL_REALIZATION.md's own pin tables. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Formato dei log V2
Regola non negoziabile (docs/v2-description.md §25-29): ogni attività
significativa (modifica, simulazione, sintesi, benchmark, decisione, errore)
deve essere registrata. Nessun log viene mai sovrascritto o troncato — solo
append. Nessun ID esperimento (EXP-XXXX) o decisione (DEC-XXXX) viene mai
riutilizzato, anche se il risultato è un FAIL.
File
development.log— log principale di sviluppo, un'entry per ogni sessione di lavoro/milestone (creazione file, refactor, avanzamento roadmap).architecture.log— decisioni e note di architettura a grana fine (non scelte finali — quelle vanno indecisions.log— ma esplorazioni, alternative considerate, vincoli scoperti).simulation.log— ogni run di simulazione (Icarus/Verilator): test, vettori, cicli, PASS/FAIL, confronto bit-exact con V1, stall/memory-wait.synthesis.log— ogni run Yosys: LUT/FF/DSP/BRAM, warning, problemi CHECK.timing.log— ogni run nextpnr-ecp5: Fmax, percorso critico, WNS/TNS se disponibili. Fmax "ufficiale" di una configurazione = solo da qui, mai da simulazione o stima.benchmark.log— tabelle di confronto per configurazione (Fmax, MAC/cycle, cycles/neuron, utilization, ecc.), sempre con etichetta THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.decisions.log— decisioni architetturali importanti, formatoDEC-XXXX(vedidocs/v2-description.md§27).experiments.log— registro principale, unEXP-XXXXper ogni esperimento end-to-end (config → sim/synth/timing → risultato), rimanda areports/experiments/EXP-XXXX/.errors.log— errori/bug/regressioni incontrati durante lo sviluppo V2 stesso (non i bug V1, già chiusi inhardware/v1/docs/validation/bugs.md).
Campi minimi per entry (§26)
timestamp, experiment_id (se applicabile), git_commit, session/agent,
module, configuration, action, reason, command, result, errors, decision,
next_action
Per synthesis/timing aggiungere: LUT, FF, DSP, BRAM, Fmax, critical path, WNS/TNS. Per simulazione: test, vectors, cycles, PASS/FAIL, bit-exact result, stall cycles, memory wait, utilization.